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ixgbe: Add hardware specific initialization code for 82599 devices

Browse source 
This patch adds the hardware initialization code specific to 82599.  This
is similar to the 82598 hardware initialization code.  It also includes all
changes to the existing hardware init code to support 82599.

Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
PJ Waskiewicz 2009-02-27 15:44:30 +00:00 committed by David S. Miller
parent 8010dc306b
commit 11afc1b1fd
8 changed files with 2927 additions and 58 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
drivers/net/ixgbe/ixgbe_82598.c
View file

@ -1046,9 +1046,9 @@ out:
*
* Determines physical layer capabilities of the current configuration.
**/
static s32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
{
s32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
switch (hw->device_id) {
case IXGBE_DEV_ID_82598:
@ -1111,8 +1111,11 @@ static struct ixgbe_mac_operations mac_ops_82598 = {
.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
.get_media_type = &ixgbe_get_media_type_82598,
.get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
.enable_rx_dma = &ixgbe_enable_rx_dma_generic,
.get_mac_addr = &ixgbe_get_mac_addr_generic,
.stop_adapter = &ixgbe_stop_adapter_generic,
.get_bus_info = &ixgbe_get_bus_info_generic,
.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
.read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
.write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
.setup_link = &ixgbe_setup_mac_link_82598,

1277
drivers/net/ixgbe/ixgbe_82599.c Normal file
View file

File diff suppressed because it is too large Load diff

319
drivers/net/ixgbe/ixgbe_common.c
View file

@ -29,6 +29,7 @@
#include <linux/delay.h>
#include <linux/sched.h>
#include "ixgbe.h"
#include "ixgbe_common.h"
#include "ixgbe_phy.h"
@ -250,6 +251,81 @@ s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
return 0;
}
/**
* ixgbe_get_bus_info_generic - Generic set PCI bus info
* @hw: pointer to hardware structure
*
* Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
**/
s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
{
struct ixgbe_adapter *adapter = hw->back;
struct ixgbe_mac_info *mac = &hw->mac;
u16 link_status;
hw->bus.type = ixgbe_bus_type_pci_express;
/* Get the negotiated link width and speed from PCI config space */
pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
&link_status);
switch (link_status & IXGBE_PCI_LINK_WIDTH) {
case IXGBE_PCI_LINK_WIDTH_1:
hw->bus.width = ixgbe_bus_width_pcie_x1;
break;
case IXGBE_PCI_LINK_WIDTH_2:
hw->bus.width = ixgbe_bus_width_pcie_x2;
break;
case IXGBE_PCI_LINK_WIDTH_4:
hw->bus.width = ixgbe_bus_width_pcie_x4;
break;
case IXGBE_PCI_LINK_WIDTH_8:
hw->bus.width = ixgbe_bus_width_pcie_x8;
break;
default:
hw->bus.width = ixgbe_bus_width_unknown;
break;
}
switch (link_status & IXGBE_PCI_LINK_SPEED) {
case IXGBE_PCI_LINK_SPEED_2500:
hw->bus.speed = ixgbe_bus_speed_2500;
break;
case IXGBE_PCI_LINK_SPEED_5000:
hw->bus.speed = ixgbe_bus_speed_5000;
break;
default:
hw->bus.speed = ixgbe_bus_speed_unknown;
break;
}
mac->ops.set_lan_id(hw);
return 0;
}
/**
* ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
* @hw: pointer to the HW structure
*
* Determines the LAN function id by reading memory-mapped registers
* and swaps the port value if requested.
**/
void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
{
struct ixgbe_bus_info *bus = &hw->bus;
u32 reg;
reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
bus->lan_id = bus->func;
/* check for a port swap */
reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
if (reg & IXGBE_FACTPS_LFS)
bus->func ^= 0x1;
}
/**
* ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
* @hw: pointer to hardware structure
@ -389,6 +465,73 @@ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
return 0;
}
/**
* ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
* @hw: pointer to hardware structure
* @offset: offset within the EEPROM to be written to
* @data: 16 bit word to be written to the EEPROM
*
* If ixgbe_eeprom_update_checksum is not called after this function, the
* EEPROM will most likely contain an invalid checksum.
**/
s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
{
s32 status;
u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
hw->eeprom.ops.init_params(hw);
if (offset >= hw->eeprom.word_size) {
status = IXGBE_ERR_EEPROM;
goto out;
}
/* Prepare the EEPROM for writing */
status = ixgbe_acquire_eeprom(hw);
if (status == 0) {
if (ixgbe_ready_eeprom(hw) != 0) {
ixgbe_release_eeprom(hw);
status = IXGBE_ERR_EEPROM;
}
}
if (status == 0) {
ixgbe_standby_eeprom(hw);
/* Send the WRITE ENABLE command (8 bit opcode ) */
ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
IXGBE_EEPROM_OPCODE_BITS);
ixgbe_standby_eeprom(hw);
/*
* Some SPI eeproms use the 8th address bit embedded in the
* opcode
*/
if ((hw->eeprom.address_bits == 8) && (offset >= 128))
write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
/* Send the Write command (8-bit opcode + addr) */
ixgbe_shift_out_eeprom_bits(hw, write_opcode,
IXGBE_EEPROM_OPCODE_BITS);
ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
hw->eeprom.address_bits);
/* Send the data */
data = (data >> 8) | (data << 8);
ixgbe_shift_out_eeprom_bits(hw, data, 16);
ixgbe_standby_eeprom(hw);
msleep(hw->eeprom.semaphore_delay);
/* Done with writing - release the EEPROM */
ixgbe_release_eeprom(hw);
}
out:
return status;
}
/**
* ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
* @hw: pointer to hardware structure
@ -1486,6 +1629,101 @@ s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
return 0;
}
/**
* ixgbe_fc_enable - Enable flow control
* @hw: pointer to hardware structure
* @packetbuf_num: packet buffer number (0-7)
*
* Enable flow control according to the current settings.
**/
s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
{
s32 ret_val = 0;
u32 mflcn_reg;
u32 fccfg_reg;
u32 reg;
mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
/*
* The possible values of fc.current_mode are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames,
* but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames but
* we do not support receiving pause frames).
* 3: Both Rx and Tx flow control (symmetric) are enabled.
* other: Invalid.
*/
switch (hw->fc.current_mode) {
case ixgbe_fc_none:
/* Flow control completely disabled by software override. */
break;
case ixgbe_fc_rx_pause:
/*
* Rx Flow control is enabled and Tx Flow control is
* disabled by software override. Since there really
* isn't a way to advertise that we are capable of RX
* Pause ONLY, we will advertise that we support both
* symmetric and asymmetric Rx PAUSE. Later, we will
* disable the adapter's ability to send PAUSE frames.
*/
mflcn_reg |= IXGBE_MFLCN_RFCE;
break;
case ixgbe_fc_tx_pause:
/*
* Tx Flow control is enabled, and Rx Flow control is
* disabled by software override.
*/
fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
break;
case ixgbe_fc_full:
/* Flow control (both Rx and Tx) is enabled by SW override. */
mflcn_reg |= IXGBE_MFLCN_RFCE;
fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
break;
default:
hw_dbg(hw, "Flow control param set incorrectly\n");
ret_val = -IXGBE_ERR_CONFIG;
goto out;
break;
}
/* Enable 802.3x based flow control settings. */
IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
/* Set up and enable Rx high/low water mark thresholds, enable XON. */
if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
if (hw->fc.send_xon)
IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num),
(hw->fc.low_water | IXGBE_FCRTL_XONE));
else
IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num),
hw->fc.low_water);
IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
(hw->fc.high_water | IXGBE_FCRTH_FCEN));
}
/* Configure pause time (2 TCs per register) */
reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
if ((packetbuf_num & 1) == 0)
reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
else
reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
out:
return ret_val;
}
/**
* ixgbe_fc_autoneg - Configure flow control
* @hw: pointer to hardware structure
@ -1624,6 +1862,74 @@ out:
return ret_val;
}
/**
* ixgbe_setup_fc_generic - Set up flow control
* @hw: pointer to hardware structure
*
* Sets up flow control.
**/
s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
{
s32 ret_val = 0;
ixgbe_link_speed speed;
bool link_up;
/* Validate the packetbuf configuration */
if (packetbuf_num < 0 || packetbuf_num > 7) {
hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
"is 0-7\n", packetbuf_num);
ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
goto out;
}
/*
* Validate the water mark configuration. Zero water marks are invalid
* because it causes the controller to just blast out fc packets.
*/
if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
hw_dbg(hw, "Invalid water mark configuration\n");
ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
goto out;
}
/*
* Validate the requested mode. Strict IEEE mode does not allow
* ixgbe_fc_rx_pause because it will cause testing anomalies.
*/
if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
"IEEE mode\n");
ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
goto out;
}
/*
* 10gig parts do not have a word in the EEPROM to determine the
* default flow control setting, so we explicitly set it to full.
*/
if (hw->fc.requested_mode == ixgbe_fc_default)
hw->fc.requested_mode = ixgbe_fc_full;
/*
* Save off the requested flow control mode for use later. Depending
* on the link partner's capabilities, we may or may not use this mode.
*/
hw->fc.current_mode = hw->fc.requested_mode;
/* Decide whether to use autoneg or not. */
hw->mac.ops.check_link(hw, &speed, &link_up, false);
if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL))
ret_val = ixgbe_fc_autoneg(hw);
if (ret_val)
goto out;
ret_val = ixgbe_fc_enable(hw, packetbuf_num);
out:
return ret_val;
}
/**
* ixgbe_disable_pcie_master - Disable PCI-express master access
* @hw: pointer to hardware structure
@ -1732,3 +2038,16 @@ void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
ixgbe_release_eeprom_semaphore(hw);
}
/**
* ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
* @hw: pointer to hardware structure
* @regval: register value to write to RXCTRL
*
* Enables the Rx DMA unit
**/
s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
{
IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
return 0;
}

10
drivers/net/ixgbe/ixgbe_common.h
View file

@ -37,12 +37,14 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num);
s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
u16 *data);
@ -61,6 +63,7 @@ s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
u32 addr_count, ixgbe_mc_addr_itr func);
s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num);
s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packtetbuf_num);
s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw);
@ -75,6 +78,13 @@ s32 ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 val);
#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
#ifndef writeq
#define writeq(val, addr) writel((u32) (val), addr); \
writel((u32) (val >> 32), (addr + 4));
#endif
#define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\

2
drivers/net/ixgbe/ixgbe_ethtool.c
View file

@ -469,7 +469,7 @@ static void ixgbe_get_regs(struct net_device *netdev,
regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT);
regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);

590
drivers/net/ixgbe/ixgbe_phy.c
View file

@ -32,6 +32,18 @@
#include "ixgbe_common.h"
#include "ixgbe_phy.h"
static void ixgbe_i2c_start(struct ixgbe_hw *hw);
static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
static bool ixgbe_get_i2c_data(u32 *i2cctl);
static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
@ -543,8 +555,9 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
u8 identifier = 0;
u8 comp_codes_1g = 0;
u8 comp_codes_10g = 0;
u8 oui_bytes[4] = {0, 0, 0, 0};
u8 oui_bytes[3] = {0, 0, 0};
u8 transmission_media = 0;
u16 enforce_sfp = 0;
status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
&identifier);
@ -564,18 +577,48 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
/* ID Module
* =========
* 0 SFP_DA_CU
* 1 SFP_SR
* 2 SFP_LR
* 0 SFP_DA_CU
* 1 SFP_SR
* 2 SFP_LR
* 3 SFP_DA_CORE0 - 82599-specific
* 4 SFP_DA_CORE1 - 82599-specific
* 5 SFP_SR/LR_CORE0 - 82599-specific
* 6 SFP_SR/LR_CORE1 - 82599-specific
*/
if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
hw->phy.sfp_type = ixgbe_sfp_type_sr;
else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
hw->phy.sfp_type = ixgbe_sfp_type_lr;
else
hw->phy.sfp_type = ixgbe_sfp_type_unknown;
if (hw->mac.type == ixgbe_mac_82598EB) {
if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
hw->phy.sfp_type = ixgbe_sfp_type_sr;
else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
hw->phy.sfp_type = ixgbe_sfp_type_lr;
else
hw->phy.sfp_type = ixgbe_sfp_type_unknown;
} else if (hw->mac.type == ixgbe_mac_82599EB) {
if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
if (hw->bus.lan_id == 0)
hw->phy.sfp_type =
ixgbe_sfp_type_da_cu_core0;
else
hw->phy.sfp_type =
ixgbe_sfp_type_da_cu_core1;
else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
if (hw->bus.lan_id == 0)
hw->phy.sfp_type =
ixgbe_sfp_type_srlr_core0;
else
hw->phy.sfp_type =
ixgbe_sfp_type_srlr_core1;
else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
if (hw->bus.lan_id == 0)
hw->phy.sfp_type =
ixgbe_sfp_type_srlr_core0;
else
hw->phy.sfp_type =
ixgbe_sfp_type_srlr_core1;
else
hw->phy.sfp_type = ixgbe_sfp_type_unknown;
}
/* Determine PHY vendor */
if (hw->phy.type == ixgbe_phy_unknown) {
@ -607,6 +650,9 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
case IXGBE_SFF_VENDOR_OUI_AVAGO:
hw->phy.type = ixgbe_phy_sfp_avago;
break;
case IXGBE_SFF_VENDOR_OUI_INTEL:
hw->phy.type = ixgbe_phy_sfp_intel;
break;
default:
if (transmission_media &
IXGBE_SFF_TWIN_AX_CAPABLE)
@ -616,7 +662,28 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
break;
}
}
status = 0;
if (hw->mac.type == ixgbe_mac_82598EB ||
(hw->phy.sfp_type != ixgbe_sfp_type_sr &&
hw->phy.sfp_type != ixgbe_sfp_type_lr &&
hw->phy.sfp_type != ixgbe_sfp_type_srlr_core0 &&
hw->phy.sfp_type != ixgbe_sfp_type_srlr_core1)) {
status = 0;
goto out;
}
hw->eeprom.ops.read(hw, IXGBE_PHY_ENFORCE_INTEL_SFP_OFFSET,
&enforce_sfp);
if (!(enforce_sfp & IXGBE_PHY_ALLOW_ANY_SFP)) {
/* Make sure we're a supported PHY type */
if (hw->phy.type == ixgbe_phy_sfp_intel) {
status = 0;
} else {
hw_dbg(hw, "SFP+ module not supported\n");
status = IXGBE_ERR_SFP_NOT_SUPPORTED;
}
} else {
status = 0;
}
}
out:
@ -651,7 +718,7 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
if ((!*list_offset) || (*list_offset == 0xFFFF))
return IXGBE_ERR_PHY;
return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
/* Shift offset to first ID word */
(*list_offset)++;
@ -687,6 +754,501 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
return 0;
}
/**
* ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
* @hw: pointer to hardware structure
* @byte_offset: EEPROM byte offset to read
* @eeprom_data: value read
*
* Performs byte read operation to SFP module's EEPROM over I2C interface.
**/
s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 *eeprom_data)
{
return hw->phy.ops.read_i2c_byte(hw, byte_offset,
IXGBE_I2C_EEPROM_DEV_ADDR,
eeprom_data);
}
/**
* ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
* @hw: pointer to hardware structure
* @byte_offset: EEPROM byte offset to write
* @eeprom_data: value to write
*
* Performs byte write operation to SFP module's EEPROM over I2C interface.
**/
s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 eeprom_data)
{
return hw->phy.ops.write_i2c_byte(hw, byte_offset,
IXGBE_I2C_EEPROM_DEV_ADDR,
eeprom_data);
}
/**
* ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to read
* @data: value read
*
* Performs byte read operation to SFP module's EEPROM over I2C interface at
* a specified deivce address.
**/
s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data)
{
s32 status = 0;
u32 max_retry = 1;
u32 retry = 0;
bool nack = 1;
do {
ixgbe_i2c_start(hw);
/* Device Address and write indication */
status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
if (status != 0)
goto fail;
status = ixgbe_get_i2c_ack(hw);
if (status != 0)
goto fail;
status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
if (status != 0)
goto fail;
status = ixgbe_get_i2c_ack(hw);
if (status != 0)
goto fail;
ixgbe_i2c_start(hw);
/* Device Address and read indication */
status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
if (status != 0)
goto fail;
status = ixgbe_get_i2c_ack(hw);
if (status != 0)
goto fail;
status = ixgbe_clock_in_i2c_byte(hw, data);
if (status != 0)
goto fail;
status = ixgbe_clock_out_i2c_bit(hw, nack);
if (status != 0)
goto fail;
ixgbe_i2c_stop(hw);
break;
fail:
ixgbe_i2c_bus_clear(hw);
retry++;
if (retry < max_retry)
hw_dbg(hw, "I2C byte read error - Retrying.\n");
else
hw_dbg(hw, "I2C byte read error.\n");
} while (retry < max_retry);
return status;
}
/**
* ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to write
* @data: value to write
*
* Performs byte write operation to SFP module's EEPROM over I2C interface at
* a specified device address.
**/
s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 data)
{
s32 status = 0;
u32 max_retry = 1;
u32 retry = 0;
do {
ixgbe_i2c_start(hw);
status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
if (status != 0)
goto fail;
status = ixgbe_get_i2c_ack(hw);
if (status != 0)
goto fail;
status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
if (status != 0)
goto fail;
status = ixgbe_get_i2c_ack(hw);
if (status != 0)
goto fail;
status = ixgbe_clock_out_i2c_byte(hw, data);
if (status != 0)
goto fail;
status = ixgbe_get_i2c_ack(hw);
if (status != 0)
goto fail;
ixgbe_i2c_stop(hw);
break;
fail:
ixgbe_i2c_bus_clear(hw);
retry++;
if (retry < max_retry)
hw_dbg(hw, "I2C byte write error - Retrying.\n");
else
hw_dbg(hw, "I2C byte write error.\n");
} while (retry < max_retry);
return status;
}
/**
* ixgbe_i2c_start - Sets I2C start condition
* @hw: pointer to hardware structure
*
* Sets I2C start condition (High -> Low on SDA while SCL is High)
**/
static void ixgbe_i2c_start(struct ixgbe_hw *hw)
{
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
/* Start condition must begin with data and clock high */
ixgbe_set_i2c_data(hw, &i2cctl, 1);
ixgbe_raise_i2c_clk(hw, &i2cctl);
/* Setup time for start condition (4.7us) */
udelay(IXGBE_I2C_T_SU_STA);
ixgbe_set_i2c_data(hw, &i2cctl, 0);
/* Hold time for start condition (4us) */
udelay(IXGBE_I2C_T_HD_STA);
ixgbe_lower_i2c_clk(hw, &i2cctl);
/* Minimum low period of clock is 4.7 us */
udelay(IXGBE_I2C_T_LOW);
}
/**
* ixgbe_i2c_stop - Sets I2C stop condition
* @hw: pointer to hardware structure
*
* Sets I2C stop condition (Low -> High on SDA while SCL is High)
**/
static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
{
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
/* Stop condition must begin with data low and clock high */
ixgbe_set_i2c_data(hw, &i2cctl, 0);
ixgbe_raise_i2c_clk(hw, &i2cctl);
/* Setup time for stop condition (4us) */
udelay(IXGBE_I2C_T_SU_STO);
ixgbe_set_i2c_data(hw, &i2cctl, 1);
/* bus free time between stop and start (4.7us)*/
udelay(IXGBE_I2C_T_BUF);
}
/**
* ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
* @hw: pointer to hardware structure
* @data: data byte to clock in
*
* Clocks in one byte data via I2C data/clock
**/
static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
{
s32 status = 0;
s32 i;
bool bit = 0;
for (i = 7; i >= 0; i--) {
status = ixgbe_clock_in_i2c_bit(hw, &bit);
*data |= bit << i;
if (status != 0)
break;
}
return status;
}
/**
* ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
* @hw: pointer to hardware structure
* @data: data byte clocked out
*
* Clocks out one byte data via I2C data/clock
**/
static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
{
s32 status = 0;
s32 i;
u32 i2cctl;
bool bit = 0;
for (i = 7; i >= 0; i--) {
bit = (data >> i) & 0x1;
status = ixgbe_clock_out_i2c_bit(hw, bit);
if (status != 0)
break;
}
/* Release SDA line (set high) */
i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
i2cctl |= IXGBE_I2C_DATA_OUT;
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
return status;
}
/**
* ixgbe_get_i2c_ack - Polls for I2C ACK
* @hw: pointer to hardware structure
*
* Clocks in/out one bit via I2C data/clock
**/
static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
{
s32 status;
u32 i = 0;
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
u32 timeout = 10;
bool ack = 1;
status = ixgbe_raise_i2c_clk(hw, &i2cctl);
if (status != 0)
goto out;
/* Minimum high period of clock is 4us */
udelay(IXGBE_I2C_T_HIGH);
/* Poll for ACK. Note that ACK in I2C spec is
* transition from 1 to 0 */
for (i = 0; i < timeout; i++) {
i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
ack = ixgbe_get_i2c_data(&i2cctl);
udelay(1);
if (ack == 0)
break;
}
if (ack == 1) {
hw_dbg(hw, "I2C ack was not received.\n");
status = IXGBE_ERR_I2C;
}
ixgbe_lower_i2c_clk(hw, &i2cctl);
/* Minimum low period of clock is 4.7 us */
udelay(IXGBE_I2C_T_LOW);
out:
return status;
}
/**
* ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
* @hw: pointer to hardware structure
* @data: read data value
*
* Clocks in one bit via I2C data/clock
**/
static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
{
s32 status;
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
status = ixgbe_raise_i2c_clk(hw, &i2cctl);
/* Minimum high period of clock is 4us */
udelay(IXGBE_I2C_T_HIGH);
i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
*data = ixgbe_get_i2c_data(&i2cctl);
ixgbe_lower_i2c_clk(hw, &i2cctl);
/* Minimum low period of clock is 4.7 us */
udelay(IXGBE_I2C_T_LOW);
return status;
}
/**
* ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
* @hw: pointer to hardware structure
* @data: data value to write
*
* Clocks out one bit via I2C data/clock
**/
static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
{
s32 status;
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
status = ixgbe_set_i2c_data(hw, &i2cctl, data);
if (status == 0) {
status = ixgbe_raise_i2c_clk(hw, &i2cctl);
/* Minimum high period of clock is 4us */
udelay(IXGBE_I2C_T_HIGH);
ixgbe_lower_i2c_clk(hw, &i2cctl);
/* Minimum low period of clock is 4.7 us.
* This also takes care of the data hold time.
*/
udelay(IXGBE_I2C_T_LOW);
} else {
status = IXGBE_ERR_I2C;
hw_dbg(hw, "I2C data was not set to %X\n", data);
}
return status;
}
/**
* ixgbe_raise_i2c_clk - Raises the I2C SCL clock
* @hw: pointer to hardware structure
* @i2cctl: Current value of I2CCTL register
*
* Raises the I2C clock line '0'->'1'
**/
static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
{
s32 status = 0;
*i2cctl |= IXGBE_I2C_CLK_OUT;
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
/* SCL rise time (1000ns) */
udelay(IXGBE_I2C_T_RISE);
return status;
}
/**
* ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
* @hw: pointer to hardware structure
* @i2cctl: Current value of I2CCTL register
*
* Lowers the I2C clock line '1'->'0'
**/
static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
{
*i2cctl &= ~IXGBE_I2C_CLK_OUT;
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
/* SCL fall time (300ns) */
udelay(IXGBE_I2C_T_FALL);
}
/**
* ixgbe_set_i2c_data - Sets the I2C data bit
* @hw: pointer to hardware structure
* @i2cctl: Current value of I2CCTL register
* @data: I2C data value (0 or 1) to set
*
* Sets the I2C data bit
**/
static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
{
s32 status = 0;
if (data)
*i2cctl |= IXGBE_I2C_DATA_OUT;
else
*i2cctl &= ~IXGBE_I2C_DATA_OUT;
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
/* Verify data was set correctly */
*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
if (data != ixgbe_get_i2c_data(i2cctl)) {
status = IXGBE_ERR_I2C;
hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
}
return status;
}
/**
* ixgbe_get_i2c_data - Reads the I2C SDA data bit
* @hw: pointer to hardware structure
* @i2cctl: Current value of I2CCTL register
*
* Returns the I2C data bit value
**/
static bool ixgbe_get_i2c_data(u32 *i2cctl)
{
bool data;
if (*i2cctl & IXGBE_I2C_DATA_IN)
data = 1;
else
data = 0;
return data;
}
/**
* ixgbe_i2c_bus_clear - Clears the I2C bus
* @hw: pointer to hardware structure
*
* Clears the I2C bus by sending nine clock pulses.
* Used when data line is stuck low.
**/
static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
{
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
u32 i;
ixgbe_set_i2c_data(hw, &i2cctl, 1);
for (i = 0; i < 9; i++) {
ixgbe_raise_i2c_clk(hw, &i2cctl);
/* Min high period of clock is 4us */
udelay(IXGBE_I2C_T_HIGH);
ixgbe_lower_i2c_clk(hw, &i2cctl);
/* Min low period of clock is 4.7us*/
udelay(IXGBE_I2C_T_LOW);
}
/* Put the i2c bus back to default state */
ixgbe_i2c_stop(hw);
}
/**
* ixgbe_check_phy_link_tnx - Determine link and speed status
* @hw: pointer to hardware structure

16
drivers/net/ixgbe/ixgbe_phy.h
View file

@ -54,14 +54,15 @@
#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
/* Bit-shift macros */
#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 12
#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 8
#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 4
#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
#define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
/* I2C SDA and SCL timing parameters for standard mode */
#define IXGBE_I2C_T_HD_STA 4
@ -101,5 +102,12 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
u16 *list_offset,
u16 *data_offset);
s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data);
s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 data);
s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 *eeprom_data);
s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 eeprom_data);
#endif /* _IXGBE_PHY_H_ */

764
drivers/net/ixgbe/ixgbe_type.h
View file

File diff suppressed because it is too large Load diff