[ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores.

There is no FSR/FAR register on no-CP15 or MPU cores. This patch adds a
dummy abort handler which returns zero for the base restored Data Abort
model !CPU_CP15_MMU cores. The abort-lv4t.S is still used with the fix-up
for the base updated Data Abort model cores.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

arch/arm/mm/Kconfig

@@ -97,7 +97,7 @@ config CPU_ARM9TDMI
 	bool "Support ARM9TDMI processor"
 	depends on !MMU
 	select CPU_32v4T
-	select CPU_ABRT_EV4T
+	select CPU_ABRT_NOMMU
 	select CPU_CACHE_V4
 	help
 	  A 32-bit RISC microprocessor based on the ARM9 processor core
@@ -192,7 +192,7 @@ config CPU_ARM940T
 	bool "Support ARM940T processor" if ARCH_INTEGRATOR
 	depends on !MMU
 	select CPU_32v4T
-	select CPU_ABRT_EV4T
+	select CPU_ABRT_NOMMU
 	select CPU_CACHE_VIVT
 	select CPU_CP15_MPU
 	help
@@ -209,7 +209,7 @@ config CPU_ARM946E
 	bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
 	depends on !MMU
 	select CPU_32v5
-	select CPU_ABRT_EV5T
+	select CPU_ABRT_NOMMU
 	select CPU_CACHE_VIVT
 	select CPU_CP15_MPU
 	help
@@ -392,6 +392,9 @@ config CPU_32v6
 	bool
 
 # The abort model
+config CPU_ABRT_NOMMU
+	bool
+
 config CPU_ABRT_EV4
 	bool
 

arch/arm/mm/Makefile

@@ -17,6 +17,7 @@ obj-$(CONFIG_MODULES)		+= proc-syms.o
 obj-$(CONFIG_ALIGNMENT_TRAP)	+= alignment.o
 obj-$(CONFIG_DISCONTIGMEM)	+= discontig.o
 
+obj-$(CONFIG_CPU_ABRT_NOMMU)	+= abort-nommu.o
 obj-$(CONFIG_CPU_ABRT_EV4)	+= abort-ev4.o
 obj-$(CONFIG_CPU_ABRT_EV4T)	+= abort-ev4t.o
 obj-$(CONFIG_CPU_ABRT_LV4T)	+= abort-lv4t.o

arch/arm/mm/abort-lv4t.S

@@ -19,11 +19,16 @@
  */
 ENTRY(v4t_late_abort)
 	tst	r3, #PSR_T_BIT			@ check for thumb mode
+#ifdef CONFIG_CPU_CP15_MMU
 	mrc	p15, 0, r1, c5, c0, 0		@ get FSR
 	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
+	bic	r1, r1, #1 << 11 | 1 << 10	@ clear bits 11 and 10 of FSR
+#else
+	mov	r0, #0				@ clear r0, r1 (no FSR/FAR)
+	mov	r1, #0
+#endif
 	bne	.data_thumb_abort
 	ldr	r8, [r2]			@ read arm instruction
-	bic	r1, r1, #1 << 11 | 1 << 10	@ clear bits 11 and 10 of FSR
 	tst	r8, #1 << 20			@ L = 1 -> write?
 	orreq	r1, r1, #1 << 11		@ yes.
 	and	r7, r8, #15 << 24

arch/arm/mm/abort-nommu.S

@@ -0,0 +1,19 @@
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+/*
+ * Function: nommu_early_abort
+ *
+ * Params  : r2 = address of aborted instruction
+ *         : r3 = saved SPSR
+ *
+ * Returns : r0 = 0 (abort address)
+ *	   : r1 = 0 (FSR)
+ *
+ * Note: There is no FSR/FAR on !CPU_CP15_MMU cores.
+ *       Just fill zero into the registers.
+ */
+	.align	5
+ENTRY(nommu_early_abort)
+	mov	r0, #0				@ clear r0, r1 (no FSR/FAR)
+	mov	r1, #0
+	mov	pc, lr

arch/arm/mm/proc-arm940.S

@@ -320,7 +320,7 @@ __arm940_setup:
  */
 	.type	arm940_processor_functions, #object
 ENTRY(arm940_processor_functions)
-	.word	v4t_early_abort
+	.word	nommu_early_abort
 	.word	cpu_arm940_proc_init
 	.word	cpu_arm940_proc_fin
 	.word	cpu_arm940_reset

arch/arm/mm/proc-arm946.S

@@ -375,7 +375,7 @@ __arm946_setup:
  */
 	.type	arm946_processor_functions, #object
 ENTRY(arm946_processor_functions)
-	.word	v5t_early_abort
+	.word	nommu_early_abort
 	.word	cpu_arm946_proc_init
 	.word	cpu_arm946_proc_fin
 	.word	cpu_arm946_reset

arch/arm/mm/proc-arm9tdmi.S

@@ -63,7 +63,7 @@ __arm9tdmi_setup:
  */
 		.type	arm9tdmi_processor_functions, #object
 ENTRY(arm9tdmi_processor_functions)
-		.word	v4t_early_abort
+		.word	nommu_early_abort
 		.word	cpu_arm9tdmi_proc_init
 		.word	cpu_arm9tdmi_proc_fin
 		.word	cpu_arm9tdmi_reset