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Staging: rtl8192su: remove RTL8192SU ifdefs

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Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Bartlomiej Zolnierkiewicz 2009-07-03 16:08:16 +02:00 committed by Greg Kroah-Hartman
parent 60083ee0c2
commit 0f29f5871c
15 changed files with 1 additions and 2792 deletions
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2
drivers/staging/rtl8192su/Makefile
View file

@ -7,8 +7,6 @@ EXTRA_CFLAGS += -mhard-float -DCONFIG_FORCE_HARD_FLOAT=y
EXTRA_CFLAGS += -DJACKSON_NEW_RX
EXTRA_CFLAGS += -DTHOMAS_BEACON
EXTRA_CFLAGS += -DRTL8192SU
#EXTRA_CFLAGS += -DMUTIPLE_BULK_OUT
r8192s_usb-objs := \

5
drivers/staging/rtl8192su/ieee80211/ieee80211_softmac_wx.c
View file

@ -230,7 +230,6 @@ int ieee80211_wx_get_rate(struct ieee80211_device *ieee,
union iwreq_data *wrqu, char *extra)
{
u32 tmp_rate = 0;
#ifdef RTL8192SU
//printk("===>mode:%d, halfNmode:%d\n", ieee->mode, ieee->bHalfWirelessN24GMode);
if (ieee->mode & (IEEE_A | IEEE_B | IEEE_G))
tmp_rate = ieee->rate;
@ -243,10 +242,6 @@ int ieee80211_wx_get_rate(struct ieee80211_device *ieee,
else
tmp_rate = HTMcsToDataRate(ieee, 15);
}
#else
tmp_rate = TxCountToDataRate(ieee, ieee->softmac_stats.CurrentShowTxate);
#endif
wrqu->bitrate.value = tmp_rate * 500000;
return 0;

4
drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c
View file

@ -495,11 +495,7 @@ void ieee80211_query_protectionmode(struct ieee80211_device* ieee, cb_desc* tcb_
{
tcb_desc->bCTSEnable = true;
tcb_desc->rts_rate = MGN_24M;
#if defined(RTL8192SU)
tcb_desc->bRTSEnable = false;
#else
tcb_desc->bRTSEnable = true;
#endif
break;
}
else if(pHTInfo->IOTAction & (HT_IOT_ACT_FORCED_RTS|HT_IOT_ACT_PURE_N_MODE))

22
drivers/staging/rtl8192su/ieee80211/rtl819x_HTProc.c
View file

@ -516,7 +516,6 @@ bool HTIOTActIsDisableMCSTwoSpatialStream(struct ieee80211_device* ieee)
//#endif
#endif
#if 1
#if defined(RTL8192SU)
PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
if(ieee->is_ap_in_wep_tkip && ieee->is_ap_in_wep_tkip(ieee->dev))
{
@ -525,7 +524,6 @@ bool HTIOTActIsDisableMCSTwoSpatialStream(struct ieee80211_device* ieee)
(pHTInfo->IOTPeer != HT_IOT_PEER_MARVELL) )
retValue = true;
}
#endif
#endif
return retValue;
}
@ -595,7 +593,6 @@ u8 HTIOTActIsForcedRTSCTS(struct ieee80211_device *ieee, struct ieee80211_networ
u8 retValue = 0;
printk("============>%s(), %d\n", __FUNCTION__, network->realtek_cap_exit);
// Force protection
#if defined(RTL8192SU)
if(ieee->pHTInfo->bCurrentHTSupport)
{
//if(!network->realtek_cap_exit)
@ -606,7 +603,6 @@ u8 HTIOTActIsForcedRTSCTS(struct ieee80211_device *ieee, struct ieee80211_networ
retValue = 1;
}
}
#endif
return retValue;
}
@ -640,7 +636,6 @@ HTIOCActRejcectADDBARequest(struct ieee80211_network *network)
//if(IS_HARDWARE_TYPE_8192SE(Adapter) ||
// IS_HARDWARE_TYPE_8192SU(Adapter)
//)
#if defined RTL8192SU
{
// Do not reject ADDBA REQ because some of the AP may
// keep on sending ADDBA REQ qhich cause DHCP fail or ping loss!
@ -650,7 +645,6 @@ HTIOCActRejcectADDBARequest(struct ieee80211_network *network)
// return FALSE;
}
#endif
return retValue;
@ -664,7 +658,6 @@ HTIOCActRejcectADDBARequest(struct ieee80211_network *network)
{
u8 retValue = 0;
//if(IS_HARDWARE_TYPE_8192SU(Adapter))
#ifdef RTL8192SU
PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
{
//#if UNDER_VISTA
@ -678,7 +671,6 @@ HTIOCActRejcectADDBARequest(struct ieee80211_network *network)
return 1;
}
#endif
return retValue;
}
@ -733,7 +725,6 @@ HTIOTActIsDisableTx40MHz(struct ieee80211_device* ieee,struct ieee80211_network
{
u8 retValue = 0;
#if defined RTL8192SU
PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
if( (KEY_TYPE_WEP104 == ieee->pairwise_key_type) ||
(KEY_TYPE_WEP40 == ieee->pairwise_key_type) ||
@ -744,7 +735,6 @@ HTIOTActIsDisableTx40MHz(struct ieee80211_device* ieee,struct ieee80211_network
if((pHTInfo->IOTPeer==HT_IOT_PEER_REALTEK) && (network->bssht.bdSupportHT))
retValue = 1;
}
#endif
return retValue;
}
@ -754,7 +744,6 @@ HTIOTActIsTxNoAggregation(struct ieee80211_device* ieee,struct ieee80211_network
{
u8 retValue = 0;
#if defined RTL8192SU
PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
if( (KEY_TYPE_WEP104 == ieee->pairwise_key_type) ||
(KEY_TYPE_WEP40 == ieee->pairwise_key_type) ||
@ -766,7 +755,6 @@ HTIOTActIsTxNoAggregation(struct ieee80211_device* ieee,struct ieee80211_network
pHTInfo->IOTPeer==HT_IOT_PEER_UNKNOWN)
retValue = 1;
}
#endif
return retValue;
}
@ -777,7 +765,6 @@ HTIOTActIsDisableTx2SS(struct ieee80211_device* ieee,struct ieee80211_network *n
{
u8 retValue = 0;
#if defined RTL8192SU
PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
if( (KEY_TYPE_WEP104 == ieee->pairwise_key_type) ||
(KEY_TYPE_WEP40 == ieee->pairwise_key_type) ||
@ -788,7 +775,6 @@ HTIOTActIsDisableTx2SS(struct ieee80211_device* ieee,struct ieee80211_network *n
if((pHTInfo->IOTPeer==HT_IOT_PEER_REALTEK) && (network->bssht.bdSupportHT))
retValue = 1;
}
#endif
return retValue;
}
@ -797,14 +783,12 @@ HTIOTActIsDisableTx2SS(struct ieee80211_device* ieee,struct ieee80211_network *n
bool HTIOCActAllowPeerAggOnePacket(struct ieee80211_device* ieee,struct ieee80211_network *network)
{
bool retValue = false;
#if defined(RTL8192SU)
PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
{
if(pHTInfo->IOTPeer == HT_IOT_PEER_MARVELL)
return true;
}
#endif
return retValue;
}
@ -1783,11 +1767,9 @@ void HTResetSelfAndSavePeerSetting(struct ieee80211_device* ieee, struct ieee80
//if(bIOTAction)
// pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_RTS;
#if defined(RTL8192SU)
bIOTAction = HTIOCActRejcectADDBARequest(pNetwork);
if(bIOTAction)
pHTInfo->IOTAction |= HT_IOT_ACT_REJECT_ADDBA_REQ;
#endif
bIOTAction = HTIOCActAllowPeerAggOnePacket(ieee, pNetwork);
if(bIOTAction)
@ -1797,7 +1779,6 @@ void HTResetSelfAndSavePeerSetting(struct ieee80211_device* ieee, struct ieee80
if(bIOTAction)
pHTInfo->IOTAction |= HT_IOT_ACT_EDCA_BIAS_ON_RX;
#if defined(RTL8192SU)
bIOTAction = HTIOTActDisableShortGI(ieee, pNetwork);
if(bIOTAction)
pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_SHORT_GI;
@ -1805,13 +1786,11 @@ void HTResetSelfAndSavePeerSetting(struct ieee80211_device* ieee, struct ieee80
bIOTAction = HTIOTActDisableHighPower(ieee, pNetwork);
if(bIOTAction)
pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_HIGH_POWER;
#endif
bIOTAction = HTIOTActIsForcedAMSDU8K(ieee, pNetwork);
if(bIOTAction)
pHTInfo->IOTAction |= HT_IOT_ACT_TX_USE_AMSDU_8K;
#if defined(RTL8192SU)
bIOTAction = HTIOTActIsTxNoAggregation(ieee, pNetwork);
if(bIOTAction)
pHTInfo->IOTAction |= HT_IOT_ACT_TX_NO_AGGREGATION;
@ -1823,7 +1802,6 @@ void HTResetSelfAndSavePeerSetting(struct ieee80211_device* ieee, struct ieee80
bIOTAction = HTIOTActIsDisableTx2SS(ieee, pNetwork);
if(bIOTAction)
pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_TX_2SS;
#endif
//must after HT_IOT_ACT_TX_NO_AGGREGATION
bIOTAction = HTIOTActIsForcedRTSCTS(ieee, pNetwork);
if(bIOTAction)

5
drivers/staging/rtl8192su/r8180_93cx6.h
View file

@ -13,13 +13,8 @@
/*This files contains card eeprom (93c46 or 93c56) programming routines*/
/*memory is addressed by WORDS*/
#ifdef RTL8192SU
#include "r8192U.h"
#include "r8192S_hw.h"
#else
#include "r8192U.h"
#include "r8192U_hw.h"
#endif
#define EPROM_DELAY 10

2
drivers/staging/rtl8192su/r8192S_Efuse.c
View file

@ -35,7 +35,6 @@
//
// In the future, we will always support EFUSE!!
//
#ifdef RTL8192SU
/*---------------------------Define Local Constant---------------------------*/
#define _POWERON_DELAY_
#define _PRE_EXECUTE_READ_CMD_
@ -2401,7 +2400,6 @@ void efuset_test_func_write(struct net_device* dev)
#endif // #if (HAL_CODE_BASE == RTL8192_S)

434
drivers/staging/rtl8192su/r8192S_firmware.c
View file

@ -11,19 +11,13 @@
* NDIS_STATUS_FAILURE - the following initialization process should be terminated
* NDIS_STATUS_SUCCESS - if firmware initialization process success
**************************************************************************************************/
#if defined(RTL8192SU)
#include "r8192U.h"
#include "r8192S_firmware.h"
#include <linux/unistd.h>
#ifdef RTL8192SU
#include "r8192S_hw.h"
#include "r8192SU_HWImg.h"
//#include "r8192S_FwImgDTM.h"
#else
//#include "r8192U_hw.h"
#include "r8192xU_firmware_img.h"
#endif
#include <linux/firmware.h>
@ -342,11 +336,9 @@ u8 FirmwareHeaderMapRfType(struct net_device *dev)
void FirmwareHeaderPriveUpdate(struct net_device *dev, PRT_8192S_FIRMWARE_PRIV pFwPriv)
{
struct r8192_priv *priv = ieee80211_priv(dev);
#ifdef RTL8192SU
// Update USB endpoint number for RQPN settings.
pFwPriv->usb_ep_num = priv->EEPROMUsbEndPointNumber; // endpoint number: 4, 6 and 11.
RT_TRACE(COMP_INIT, "FirmwarePriveUpdate(): usb_ep_num(%#x)\n", pFwPriv->usb_ep_num);
#endif
// Update RF types for RATR settings.
pFwPriv->rf_config = FirmwareHeaderMapRfType(dev);
@ -551,430 +543,4 @@ bool FirmwareDownload92S(struct net_device *dev)
rtStatus = false;
return rtStatus;
}
#else
void firmware_init_param(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
rt_firmware *pfirmware = priv->pFirmware;
pfirmware->cmdpacket_frag_thresold = GET_COMMAND_PACKET_FRAG_THRESHOLD(MAX_TRANSMIT_BUFFER_SIZE);
}
/*
* segment the img and use the ptr and length to remember info on each segment
*
*/
bool fw_download_code(struct net_device *dev, u8 *code_virtual_address, u32 buffer_len)
{
struct r8192_priv *priv = ieee80211_priv(dev);
bool rt_status = true;
//u16 frag_threshold;
u16 frag_length, frag_offset = 0;
//u16 total_size;
int i;
//rt_firmware *pfirmware = priv->pFirmware;
struct sk_buff *skb;
unsigned char *seg_ptr;
cb_desc *tcb_desc;
u8 bLastIniPkt;
#ifndef RTL8192SU
if(buffer_len >= 64000-USB_HWDESC_HEADER_LEN)
{
return rt_status;
}
firmware_init_param(dev);
//Fragmentation might be required
frag_threshold = pfirmware->cmdpacket_frag_thresold;
#endif
do {
#ifndef RTL8192SU
if((buffer_len - frag_offset) > frag_threshold) {
frag_length = frag_threshold ;
bLastIniPkt = 0;
} else
#endif
{
frag_length = buffer_len - frag_offset;
bLastIniPkt = 1;
}
/* Allocate skb buffer to contain firmware info and tx descriptor info
* add 4 to avoid packet appending overflow.
* */
#ifdef RTL8192U
skb = dev_alloc_skb(USB_HWDESC_HEADER_LEN + frag_length + 4);
#else
skb = dev_alloc_skb(frag_length + 4);
#endif
memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE);
tcb_desc->queue_index = TXCMD_QUEUE;
tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT;
tcb_desc->bLastIniPkt = bLastIniPkt;
#ifdef RTL8192U
skb_reserve(skb, USB_HWDESC_HEADER_LEN);
#endif
seg_ptr = skb->data;
/*
* Transform from little endian to big endian
* and pending zero
*/
for(i=0 ; i < frag_length; i+=4) {
*seg_ptr++ = ((i+0)<frag_length)?code_virtual_address[i+3]:0;
*seg_ptr++ = ((i+1)<frag_length)?code_virtual_address[i+2]:0;
*seg_ptr++ = ((i+2)<frag_length)?code_virtual_address[i+1]:0;
*seg_ptr++ = ((i+3)<frag_length)?code_virtual_address[i+0]:0;
}
tcb_desc->txbuf_size= (u16)i;
skb_put(skb, i);
if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)||
(!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\
(priv->ieee80211->queue_stop) ) {
RT_TRACE(COMP_FIRMWARE,"=====================================================> tx full!\n");
skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb);
} else {
priv->ieee80211->softmac_hard_start_xmit(skb,dev);
}
code_virtual_address += frag_length;
frag_offset += frag_length;
}while(frag_offset < buffer_len);
return rt_status;
#if 0
cmdsend_downloadcode_fail:
rt_status = false;
RT_TRACE(COMP_ERR, "CmdSendDownloadCode fail !!\n");
return rt_status;
#endif
}
bool
fwSendNullPacket(
struct net_device *dev,
u32 Length
)
{
bool rtStatus = true;
struct r8192_priv *priv = ieee80211_priv(dev);
struct sk_buff *skb;
cb_desc *tcb_desc;
unsigned char *ptr_buf;
bool bLastInitPacket = false;
//PlatformAcquireSpinLock(dev, RT_TX_SPINLOCK);
//Get TCB and local buffer from common pool. (It is shared by CmdQ, MgntQ, and USB coalesce DataQ)
skb = dev_alloc_skb(Length+ 4);
memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE);
tcb_desc->queue_index = TXCMD_QUEUE;
tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT;
tcb_desc->bLastIniPkt = bLastInitPacket;
ptr_buf = skb_put(skb, Length);
memset(ptr_buf,0,Length);
tcb_desc->txbuf_size= (u16)Length;
if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)||
(!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\
(priv->ieee80211->queue_stop) ) {
RT_TRACE(COMP_FIRMWARE,"===================NULL packet==================================> tx full!\n");
skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb);
} else {
priv->ieee80211->softmac_hard_start_xmit(skb,dev);
}
//PlatformReleaseSpinLock(dev, RT_TX_SPINLOCK);
return rtStatus;
}
//-----------------------------------------------------------------------------
// Procedure: Check whether main code is download OK. If OK, turn on CPU
//
// Description: CPU register locates in different page against general register.
// Switch to CPU register in the begin and switch back before return
//
//
// Arguments: The pointer of the dev
//
// Returns:
// NDIS_STATUS_FAILURE - the following initialization process should be terminated
// NDIS_STATUS_SUCCESS - if firmware initialization process success
//-----------------------------------------------------------------------------
bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev)
{
bool rt_status = true;
int check_putcodeOK_time = 200000, check_bootOk_time = 200000;
u32 CPU_status = 0;
/* Check whether put code OK */
do {
CPU_status = read_nic_dword(dev, CPU_GEN);
if(CPU_status&CPU_GEN_PUT_CODE_OK)
break;
}while(check_putcodeOK_time--);
if(!(CPU_status&CPU_GEN_PUT_CODE_OK)) {
RT_TRACE(COMP_ERR, "Download Firmware: Put code fail!\n");
goto CPUCheckMainCodeOKAndTurnOnCPU_Fail;
} else {
RT_TRACE(COMP_FIRMWARE, "Download Firmware: Put code ok!\n");
}
/* Turn On CPU */
CPU_status = read_nic_dword(dev, CPU_GEN);
write_nic_byte(dev, CPU_GEN, (u8)((CPU_status|CPU_GEN_PWR_STB_CPU)&0xff));
mdelay(1000);
/* Check whether CPU boot OK */
do {
CPU_status = read_nic_dword(dev, CPU_GEN);
if(CPU_status&CPU_GEN_BOOT_RDY)
break;
}while(check_bootOk_time--);
if(!(CPU_status&CPU_GEN_BOOT_RDY)) {
goto CPUCheckMainCodeOKAndTurnOnCPU_Fail;
} else {
RT_TRACE(COMP_FIRMWARE, "Download Firmware: Boot ready!\n");
}
return rt_status;
CPUCheckMainCodeOKAndTurnOnCPU_Fail:
RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__);
rt_status = FALSE;
return rt_status;
}
bool CPUcheck_firmware_ready(struct net_device *dev)
{
bool rt_status = true;
int check_time = 200000;
u32 CPU_status = 0;
/* Check Firmware Ready */
do {
CPU_status = read_nic_dword(dev, CPU_GEN);
if(CPU_status&CPU_GEN_FIRM_RDY)
break;
}while(check_time--);
if(!(CPU_status&CPU_GEN_FIRM_RDY))
goto CPUCheckFirmwareReady_Fail;
else
RT_TRACE(COMP_FIRMWARE, "Download Firmware: Firmware ready!\n");
return rt_status;
CPUCheckFirmwareReady_Fail:
RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__);
rt_status = false;
return rt_status;
}
bool init_firmware(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
bool rt_status = TRUE;
u8 *firmware_img_buf[3] = { &rtl8190_fwboot_array[0],
&rtl8190_fwmain_array[0],
&rtl8190_fwdata_array[0]};
u32 firmware_img_len[3] = { sizeof(rtl8190_fwboot_array),
sizeof(rtl8190_fwmain_array),
sizeof(rtl8190_fwdata_array)};
u32 file_length = 0;
u8 *mapped_file = NULL;
u32 init_step = 0;
opt_rst_type_e rst_opt = OPT_SYSTEM_RESET;
firmware_init_step_e starting_state = FW_INIT_STEP0_BOOT;
rt_firmware *pfirmware = priv->pFirmware;
const struct firmware *fw_entry;
const char *fw_name[3] = { "RTL8192U/boot.img",
"RTL8192U/main.img",
"RTL8192U/data.img"};
int rc;
RT_TRACE(COMP_FIRMWARE, " PlatformInitFirmware()==>\n");
if (pfirmware->firmware_status == FW_STATUS_0_INIT ) {
/* it is called by reset */
rst_opt = OPT_SYSTEM_RESET;
starting_state = FW_INIT_STEP0_BOOT;
// TODO: system reset
}else if(pfirmware->firmware_status == FW_STATUS_5_READY) {
/* it is called by Initialize */
rst_opt = OPT_FIRMWARE_RESET;
starting_state = FW_INIT_STEP2_DATA;
}else {
RT_TRACE(COMP_FIRMWARE, "PlatformInitFirmware: undefined firmware state\n");
}
/*
* Download boot, main, and data image for System reset.
* Download data image for firmware reseta
*/
priv->firmware_source = FW_SOURCE_IMG_FILE;
for(init_step = starting_state; init_step <= FW_INIT_STEP2_DATA; init_step++) {
/*
* Open Image file, and map file to contineous memory if open file success.
* or read image file from array. Default load from IMG file
*/
if(rst_opt == OPT_SYSTEM_RESET) {
switch(priv->firmware_source) {
case FW_SOURCE_IMG_FILE:
rc = request_firmware(&fw_entry, fw_name[init_step],&priv->udev->dev);
if(rc < 0 ) {
RT_TRACE(COMP_ERR, "request firmware fail!\n");
goto download_firmware_fail;
}
if(fw_entry->size > sizeof(pfirmware->firmware_buf)) {
RT_TRACE(COMP_ERR, "img file size exceed the container buffer fail!\n");
goto download_firmware_fail;
}
if(init_step != FW_INIT_STEP1_MAIN) {
memcpy(pfirmware->firmware_buf,fw_entry->data,fw_entry->size);
mapped_file = pfirmware->firmware_buf;
file_length = fw_entry->size;
} else {
#ifdef RTL8190P
memcpy(pfirmware->firmware_buf,fw_entry->data,fw_entry->size);
mapped_file = pfirmware->firmware_buf;
file_length = fw_entry->size;
#else
memset(pfirmware->firmware_buf,0,128);
memcpy(&pfirmware->firmware_buf[128],fw_entry->data,fw_entry->size);
mapped_file = pfirmware->firmware_buf;
file_length = fw_entry->size + 128;
#endif
}
pfirmware->firmware_buf_size = file_length;
break;
case FW_SOURCE_HEADER_FILE:
mapped_file = firmware_img_buf[init_step];
file_length = firmware_img_len[init_step];
if(init_step == FW_INIT_STEP2_DATA) {
memcpy(pfirmware->firmware_buf, mapped_file, file_length);
pfirmware->firmware_buf_size = file_length;
}
break;
default:
break;
}
}else if(rst_opt == OPT_FIRMWARE_RESET ) {
/* we only need to download data.img here */
mapped_file = pfirmware->firmware_buf;
file_length = pfirmware->firmware_buf_size;
}
/* Download image file */
/* The firmware download process is just as following,
* 1. that is each packet will be segmented and inserted to the wait queue.
* 2. each packet segment will be put in the skb_buff packet.
* 3. each skb_buff packet data content will already include the firmware info
* and Tx descriptor info
* */
rt_status = fw_download_code(dev,mapped_file,file_length);
if(rst_opt == OPT_SYSTEM_RESET) {
release_firmware(fw_entry);
}
if(rt_status != TRUE) {
goto download_firmware_fail;
}
switch(init_step) {
case FW_INIT_STEP0_BOOT:
/* Download boot
* initialize command descriptor.
* will set polling bit when firmware code is also configured
*/
pfirmware->firmware_status = FW_STATUS_1_MOVE_BOOT_CODE;
#ifdef RTL8190P
// To initialize IMEM, CPU move code from 0x80000080, hence, we send 0x80 byte packet
rt_status = fwSendNullPacket(dev, RTL8190_CPU_START_OFFSET);
if(rt_status != true)
{
RT_TRACE(COMP_INIT, "fwSendNullPacket() fail ! \n");
goto download_firmware_fail;
}
#endif
//mdelay(1000);
/*
* To initialize IMEM, CPU move code from 0x80000080,
* hence, we send 0x80 byte packet
*/
break;
case FW_INIT_STEP1_MAIN:
/* Download firmware code. Wait until Boot Ready and Turn on CPU */
pfirmware->firmware_status = FW_STATUS_2_MOVE_MAIN_CODE;
/* Check Put Code OK and Turn On CPU */
rt_status = CPUcheck_maincodeok_turnonCPU(dev);
if(rt_status != TRUE) {
RT_TRACE(COMP_ERR, "CPUcheck_maincodeok_turnonCPU fail!\n");
goto download_firmware_fail;
}
pfirmware->firmware_status = FW_STATUS_3_TURNON_CPU;
break;
case FW_INIT_STEP2_DATA:
/* download initial data code */
pfirmware->firmware_status = FW_STATUS_4_MOVE_DATA_CODE;
mdelay(1);
rt_status = CPUcheck_firmware_ready(dev);
if(rt_status != TRUE) {
RT_TRACE(COMP_ERR, "CPUcheck_firmware_ready fail(%d)!\n",rt_status);
goto download_firmware_fail;
}
/* wait until data code is initialized ready.*/
pfirmware->firmware_status = FW_STATUS_5_READY;
break;
}
}
RT_TRACE(COMP_FIRMWARE, "Firmware Download Success\n");
//assert(pfirmware->firmware_status == FW_STATUS_5_READY, ("Firmware Download Fail\n"));
return rt_status;
download_firmware_fail:
RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__);
rt_status = FALSE;
return rt_status;
}
#endif

2
drivers/staging/rtl8192su/r8192S_hw.h
View file

@ -49,10 +49,8 @@ typedef enum _RT_RF_TYPE_DEFINITION
RF_1T2R = 0,
RF_2T4R,
RF_2T2R,
#ifdef RTL8192SU
RF_1T1R,
RF_2T2R_GREEN,
#endif
//RF_3T3R,
//RF_3T4R,
//RF_4T4R,

95
drivers/staging/rtl8192su/r8192S_phy.c
View file

@ -35,17 +35,11 @@
#include "r8192U_dm.h"
#include "r8192S_rtl6052.h"
#ifdef RTL8192SU
#include "r8192S_hw.h"
#include "r8192S_phy.h"
#include "r8192S_phyreg.h"
#include "r8192SU_HWImg.h"
//#include "r8192S_FwImgDTM.h"
#else
#include "r8192U_hw.h"
#include "r819xU_phy.h"
#include "r819xU_phyreg.h"
#endif
#include "ieee80211/dot11d.h"
@ -58,26 +52,6 @@
/*------------------------Define local variable------------------------------*/
// 2004-05-11
#ifndef RTL8192SU
static u32 RF_CHANNEL_TABLE_ZEBRA[]={
0,
0x085c,//2412 1
0x08dc,//2417 2
0x095c,//2422 3
0x09dc,//2427 4
0x0a5c,//2432 5
0x0adc,//2437 6
0x0b5c,//2442 7
0x0bdc,//2447 8
0x0c5c,//2452 9
0x0cdc,//2457 10
0x0d5c,//2462 11
0x0ddc,//2467 12
0x0e5c,//2472 13
//0x0f5c,//2484
0x0f72,//2484 //20040810
};
#endif
static u32
phy_CalculateBitShift(u32 BitMask);
@ -114,7 +88,6 @@ static u8 phy_DbmToTxPwrIdx( struct net_device* dev, WIRELESS_MODE WirelessMode,
void phy_SetFwCmdIOCallback(struct net_device* dev);
//#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
#ifdef RTL8192SU
//
// Description:
// Base Band read by 4181 to make sure that operation could be done in unlimited cycle.
@ -382,7 +355,6 @@ void phy_SetUsbRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 RegAdd
}
#endif
/*---------------------Define local function prototype-----------------------*/
@ -422,7 +394,6 @@ u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask)
// 2008.09.06.
//
//#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
#ifdef RTL8192SU
if(IS_BB_REG_OFFSET_92S(RegAddr))
{
//if(RT_USB_CANNOT_IO(Adapter)) return FALSE;
@ -436,7 +407,6 @@ u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask)
OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
}
else
#endif
{
OriginalValue = read_nic_dword(dev, RegAddr);
}
@ -482,7 +452,6 @@ void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data
// 2008.09.06.
//
//#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
#ifdef RTL8192SU
if(IS_BB_REG_OFFSET_92S(RegAddr))
{
if((RegAddr & 0x03) != 0)
@ -501,7 +470,6 @@ void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data
phy_SetUsbBBReg(dev, RegAddr, Data);
}
else
#endif
{
if(BitMask!= bMaskDWord)
{//if not "double word" write
@ -571,19 +539,8 @@ u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u3
// 2008.09.06.
//
//#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
#ifdef RTL8192SU
//if(RT_USB_CANNOT_IO(Adapter)) return FALSE;
Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
#else
if (priv->Rf_Mode == RF_OP_By_FW)
{
Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
}
else
{
Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr);
}
#endif
BitShift = phy_CalculateBitShift(BitMask);
Readback_Value = (Original_Value & BitMask) >> BitShift;
@ -647,7 +604,6 @@ void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32
// 2008.09.06.
//
//#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
#ifdef RTL8192SU
//if(RT_USB_CANNOT_IO(Adapter)) return;
if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
@ -659,37 +615,6 @@ void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32
}
else
phy_SetUsbRFReg(dev, eRFPath, RegAddr, Data);
#else
if (priv->Rf_Mode == RF_OP_By_FW)
{
//DbgPrint("eRFPath-%d Addr[%02x] = %08x\n", eRFPath, RegAddr, Data);
if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
{
Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
BitShift = phy_CalculateBitShift(BitMask);
New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
}
else
phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
}
else
{
//DbgPrint("eRFPath-%d Addr[%02x] = %08x\n", eRFPath, RegAddr, Data);
if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
{
Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr);
BitShift = phy_CalculateBitShift(BitMask);
New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
}
else
phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
}
#endif
//PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
//spin_unlock_irqrestore(&priv->rf_lock, flags); //YJ,test,090113
up(&priv->rf_sem);
@ -1477,11 +1402,7 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E
if(Rtl819XRadioA_Array_Table[i] == 0xfe)
{ // Deay specific ms. Only RF configuration require delay.
//#if (DEV_BUS_TYPE == USB_INTERFACE)
#ifdef RTL8192SU
mdelay(1000);
#else
mdelay(50);
#endif
}
else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
mdelay(5);
@ -1505,11 +1426,7 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E
if(Rtl819XRadioB_Array_Table[i] == 0xfe)
{ // Deay specific ms. Only RF configuration require delay.
//#if (DEV_BUS_TYPE == USB_INTERFACE)
#ifdef RTL8192SU
mdelay(1000);
#else
mdelay(50);
#endif
}
else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
mdelay(5);
@ -2969,9 +2886,7 @@ void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EX
#endif
if((priv->up) )// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower) )
{
#if defined(RTL8192SU)
SetBWModeCallback8192SUsbWorkItem(dev);
#endif
}
else
{
@ -3086,9 +3001,7 @@ u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
if((priv->up))// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower))
{
#if defined(RTL8192SU)
SwChnlCallback8192SUsbWorkItem(dev);
#endif
#ifdef TO_DO_LIST
if(bResult)
{
@ -3339,13 +3252,9 @@ phy_SwChnlStepByStep(
case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
{
#if defined RTL8192SU
// For new T65 RF 0222d register 0x18 bit 0-9 = channel number.
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f, (CurrentCmd->Para2));
//printk("====>%x, %x, read_back:%x\n", CurrentCmd->Para2,CurrentCmd->Para1, rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f));
#else
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, ((CurrentCmd->Para2)<<7));
#endif
}
break;
default:
@ -3813,7 +3722,6 @@ extern void PHY_IQCalibrateBcut(struct net_device* dev)
//
//-------------------------Move to other DIR later----------------------------*/
//#if (DEV_BUS_TYPE == USB_INTERFACE)
#ifdef RTL8192SU
// use in phy only (in win it's timer)
void SwChnlCallback8192SUsb(struct net_device *dev)
@ -4190,7 +4098,6 @@ void SetBWModeCallback8192SUsbWorkItem(struct net_device *dev)
}
//--------------------------Move to oter DIR later-------------------------------*/
#ifdef RTL8192SU
void InitialGain8192S(struct net_device *dev, u8 Operation)
{
#ifdef TO_DO_LIST
@ -4198,7 +4105,6 @@ void InitialGain8192S(struct net_device *dev, u8 Operation)
#endif
}
#endif
void InitialGain819xUsb(struct net_device *dev, u8 Operation)
{
@ -4284,7 +4190,6 @@ extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
}
}
#endif // #if (DEV_BUS_TYPE == USB_INTERFACE)
//-----------------------------------------------------------------------------
// Description:

27
drivers/staging/rtl8192su/r8192S_rtl6052.c
View file

@ -23,15 +23,9 @@
#include "r8192U.h"
#include "r8192S_rtl6052.h"
#ifdef RTL8192SU
#include "r8192S_hw.h"
#include "r8192S_phyreg.h"
#include "r8192S_phy.h"
#else
#include "r8192U_hw.h"
#include "r819xU_phyreg.h"
#include "r819xU_phy.h"
#endif
/*---------------------------Define Local Constant---------------------------*/
@ -162,7 +156,6 @@ void PHY_RF6052SetBandwidth(struct net_device* dev, HT_CHANNEL_WIDTH Bandwidth)
//if (priv->card_8192 == NIC_8192SE)
#ifdef RTL8192SU //YJ,test,090113
{
switch(Bandwidth)
{
@ -184,26 +177,6 @@ void PHY_RF6052SetBandwidth(struct net_device* dev, HT_CHANNEL_WIDTH Bandwidth)
}
}
// else
#else
{
for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
{
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
//PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x01);
break;
case HT_CHANNEL_WIDTH_20_40:
//PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x00);
break;
default:
RT_TRACE(COMP_DBG, "PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
break;
}
}
}
#endif
}

190
drivers/staging/rtl8192su/r8192U.h
View file

@ -42,11 +42,7 @@
#include "ieee80211/ieee80211.h"
#ifdef RTL8192SU
#include "r8192S_firmware.h"
#else
#include "r819xU_firmware.h"
#endif
//#define RTL8192U
#define RTL819xU_MODULE_NAME "rtl819xU"
@ -305,7 +301,6 @@ do { if(rt_global_debug_component & component) \
#define OFDM_Table_Length 19
#define CCK_Table_length 12
#ifdef RTL8192SU
//
//Tx Descriptor for RLT8192SU(Normal mode)
//
@ -423,51 +418,9 @@ typedef struct _tx_status_desc_8192s_usb{
u8 RxAGC3;
u8 RxAGC4;
}tx_status_desc_8192s_usb, *ptx_status_desc_8192s_usb;
#else
/* for rtl819x */
typedef struct _tx_desc_819x_usb {
//DWORD 0
u16 PktSize;
u8 Offset;
u8 Reserved0:3;
u8 CmdInit:1;
u8 LastSeg:1;
u8 FirstSeg:1;
u8 LINIP:1;
u8 OWN:1;
//DWORD 1
u8 TxFWInfoSize;
u8 RATid:3;
u8 DISFB:1;
u8 USERATE:1;
u8 MOREFRAG:1;
u8 NoEnc:1;
u8 PIFS:1;
u8 QueueSelect:5;
u8 NoACM:1;
u8 Reserved1:2;
u8 SecCAMID:5;
u8 SecDescAssign:1;
u8 SecType:2;
//DWORD 2
u16 TxBufferSize;
//u16 Reserved2;
u8 ResvForPaddingLen:7;
u8 Reserved3:1;
u8 Reserved4;
//DWORD 3, 4, 5
u32 Reserved5;
u32 Reserved6;
u32 Reserved7;
}tx_desc_819x_usb, *ptx_desc_819x_usb;
#endif
#ifdef RTL8192SU
//
//Tx Descriptor for RLT8192SU(Load FW mode)
//
@ -532,39 +485,7 @@ typedef struct _tx_h2c_cmd_hdr_8192s_usb{
// DWORD 1
u32 Rsvd0;
}tx_h2c_cmd_hdr_8192s_usb, *ptx_h2c_cmd_hdr_8192s_usb;
#else
typedef struct _tx_desc_cmd_819x_usb {
//DWORD 0
u16 Reserved0;
u8 Reserved1;
u8 Reserved2:3;
u8 CmdInit:1;
u8 LastSeg:1;
u8 FirstSeg:1;
u8 LINIP:1;
u8 OWN:1;
//DOWRD 1
//u32 Reserved3;
u8 TxFWInfoSize;
u8 Reserved3;
u8 QueueSelect;
u8 Reserved4;
//DOWRD 2
u16 TxBufferSize;
u16 Reserved5;
//DWORD 3,4,5
//u32 TxBufferAddr;
//u32 NextDescAddress;
u32 Reserved6;
u32 Reserved7;
u32 Reserved8;
}tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
#endif
#ifdef RTL8192SU
typedef struct _tx_fwinfo_819x_usb{
//DWORD 0
u8 TxRate:7;
@ -593,38 +514,6 @@ typedef struct _tx_fwinfo_819x_usb{
u32 Tx_INFO_RSVD:6;
u32 PacketID:13;
}tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
#else
typedef struct _tx_fwinfo_819x_usb {
//DOWRD 0
u8 TxRate:7;
u8 CtsEnable:1;
u8 RtsRate:7;
u8 RtsEnable:1;
u8 TxHT:1;
u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
u8 TxBandwidth:1; // This is used for HT MCS rate only.
u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
u8 STBC:2;
u8 AllowAggregation:1;
u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
u8 RtsBandwidth:1; // This is used for HT MCS rate only.
u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
u8 RtsSTBC:2;
u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
//DWORD 1
u32 RxMF:2;
u32 RxAMD:3;
u32 TxPerPktInfoFeedback:1;//1 indicate Tx info gathtered by firmware and returned by Rx Cmd
u32 Reserved1:2;
u32 TxAGCOffSet:4;
u32 TxAGCSign:1;
u32 Tx_INFO_RSVD:6;
u32 PacketID:13;
//u32 Reserved;
}tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
#endif
typedef struct rtl8192_rx_info {
struct urb *urb;
@ -632,7 +521,6 @@ typedef struct rtl8192_rx_info {
u8 out_pipe;
}rtl8192_rx_info ;
#ifdef RTL8192SU
//typedef struct _RX_DESC_STATUS_8192SU{
typedef struct rx_desc_819x_usb{
//DWORD 0
@ -695,36 +583,8 @@ typedef struct rx_desc_819x_usb{
u32 TSFL;
//}RX_DESC_STATUS_8192SU, *PRX_DESC_STATUS_8192SU;
}rx_desc_819x_usb, *prx_desc_819x_usb;
#else
typedef struct rx_desc_819x_usb{
//DOWRD 0
u16 Length:14;
u16 CRC32:1;
u16 ICV:1;
u8 RxDrvInfoSize;
u8 Shift:2;
u8 PHYStatus:1;
u8 SWDec:1;
//u8 LastSeg:1;
//u8 FirstSeg:1;
//u8 EOR:1;
//u8 OWN:1;
u8 Reserved1:4;
//DWORD 1
u32 Reserved2;
//DWORD 2
//u32 Reserved3;
//DWORD 3
//u32 BufferAddress;
}rx_desc_819x_usb, *prx_desc_819x_usb;
#endif
#ifdef RTL8192SU
//
// Driver info are written to the begining of the RxBuffer
//
@ -800,41 +660,11 @@ typedef struct rx_drvinfo_819x_usb{
u8 reserve:4;
}rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
#else
typedef struct rx_drvinfo_819x_usb{
//DWORD 0
u16 Reserved1:12;
u16 PartAggr:1;
u16 FirstAGGR:1;
u16 Reserved2:2;
u8 RxRate:7;
u8 RxHT:1;
u8 BW:1;
u8 SPLCP:1;
u8 Reserved3:2;
u8 PAM:1;
u8 Mcast:1;
u8 Bcast:1;
u8 Reserved4:1;
//DWORD 1
u32 TSFL;
}rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
#endif
#define HWSET_MAX_SIZE_92S 128
#ifdef RTL8192SU
#define MAX_802_11_HEADER_LENGTH 40
#define MAX_PKT_AGG_NUM 256
#define TX_PACKET_SHIFT_BYTES USB_HWDESC_HEADER_LEN
#else
#define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
#define MAX_PKT_AGG_NUM 64
#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
#endif
#define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */
#define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/
@ -908,7 +738,6 @@ typedef struct _rt_firmare_seg_container {
u8 *seg_ptr;
}fw_seg_container, *pfw_seg_container;
#ifdef RTL8192SU
//--------------------------------------------------------------------------------
// 8192S Firmware related
//--------------------------------------------------------------------------------
@ -1006,16 +835,6 @@ typedef struct _rt_firmware{
//u16 firmware_buf_size;//in 92u temp FIXLZM
}rt_firmware, *prt_firmware;
#else
typedef struct _rt_firmware{
firmware_status_e firmware_status;
u16 cmdpacket_frag_thresold;
#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
#define MAX_FW_INIT_STEP 3
u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
u16 firmware_buf_size[MAX_FW_INIT_STEP];
}rt_firmware, *prt_firmware;
#endif
typedef struct _rt_firmware_info_819xUsb{
u8 sz_info[16];
}rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
@ -1659,11 +1478,7 @@ typedef struct r8192_priv
/*PHY related*/
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
// Read/write are allow for following hardware information variables
#ifdef RTL8192SU
u32 MCSTxPowerLevelOriginalOffset[7];//FIXLZM
#else
u32 MCSTxPowerLevelOriginalOffset[6];
#endif
u32 CCKTxPowerLevelOriginalOffset;
u8 TxPowerLevelCCK[14]; // CCK channel 1~14
u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
@ -1945,14 +1760,9 @@ struct ssid_thread {
};
#endif
#ifdef RTL8192SU
short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb);
bool FirmwareDownload92S(struct net_device *dev);
#else
short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
bool init_firmware(struct net_device *dev);
#endif
short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);

1738
drivers/staging/rtl8192su/r8192U_core.c
View file

File diff suppressed because it is too large Load diff

178
drivers/staging/rtl8192su/r8192U_dm.c
View file

@ -15,7 +15,6 @@ Major Change History:
--*/
#ifdef RTL8192SU
#include "r8192U.h"
#include "r8192U_dm.h"
//#include "r8190_rtl8256.h"
@ -23,15 +22,6 @@ Major Change History:
#include "r8192S_hw.h"
#include "r8192S_phy.h"
#include "r8192S_phyreg.h"
#else
#include "r8192U.h"
#include "r8192U_dm.h"
#include "r8192U_hw.h"
#include "r819xU_phy.h"
#include "r819xU_phyreg.h"
#include "r8190_rtl8256.h"
#include "r819xU_cmdpkt.h"
#endif
/*---------------------------Define Local Constant---------------------------*/
//
@ -50,7 +40,6 @@ typedef enum _HT_IOT_PEER
}HT_IOT_PEER_E, *PHTIOT_PEER_E;
#endif
#if 1
#ifdef RTL8192SU
static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
// UNKNOWN REALTEK_90 /*REALTEK_92SE*/ BROADCOM RALINK ATHEROS CISCO MARVELL 92U_AP SELF_AP
{ 0xa44f, 0x5ea44f, 0x5ea44f, 0xa44f, 0xa44f, 0xa44f, 0xa630, 0xa42b, 0x5e4322, 0x5e4322};
@ -58,14 +47,6 @@ typedef enum _HT_IOT_PEER
// UNKNOWN REALTEK /*REALTEK_92SE*/ BROADCOM RALINK ATHEROS CISCO MARVELL 92U_AP SELF_AP
{ 0x5ea44f, 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea422, 0x5e4322, 0x3ea44f, 0x5ea42b, 0x5e4322, 0x5e4322};
#else
static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
{ 0x5e4322, 0x5e4322, 0x5ea44f, 0x5e4322, 0x604322, 0xa44f, 0x5ea44f};
static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
{ 0x5e4322, 0xa44f, 0x5ea44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f};
#endif
#endif
#define RTK_UL_EDCA 0xa44f
@ -202,7 +183,6 @@ static void dm_ctstoself(struct net_device *dev);
//================================================================================
// HW Dynamic mechanism interface.
//================================================================================
#ifdef RTL8192SU
static void dm_CheckAggrPolicy(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
@ -273,7 +253,6 @@ static void dm_CheckAggrPolicy(struct net_device *dev)
lastTxOkCnt = priv->stats.txbytesunicast;
lastRxOkCnt = priv->stats.rxbytesunicast;
}
#endif
//
// Description:
// Prepare SW resource for HW dynamic mechanism.
@ -293,11 +272,7 @@ init_hal_dm(struct net_device *dev)
//Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
dm_init_dynamic_txpower(dev);
init_rate_adaptive(dev);
#ifdef RTL8192SU
dm_initialize_txpower_tracking(dev);
#else
//dm_initialize_txpower_tracking(dev);
#endif
dm_dig_init(dev);
dm_init_edca_turbo(dev);
dm_init_bandwidth_autoswitch(dev);
@ -317,7 +292,6 @@ extern void deinit_hal_dm(struct net_device *dev)
#ifdef RTL8192SU
//#if 0
extern void hal_dm_watchdog(struct net_device *dev)
{
@ -372,31 +346,6 @@ extern void hal_dm_watchdog(struct net_device *dev)
dm_ctstoself(dev);
} //HalDmWatchDog
#else
extern void hal_dm_watchdog(struct net_device *dev)
{
//struct r8192_priv *priv = ieee80211_priv(dev);
//static u8 previous_bssid[6] ={0};
/*Add by amy 2008/05/15 ,porting from windows code.*/
dm_check_rate_adaptive(dev);
dm_dynamic_txpower(dev);
dm_check_txrateandretrycount(dev);
dm_check_txpower_tracking(dev);
dm_ctrl_initgain_byrssi(dev);
dm_check_edca_turbo(dev);
dm_bandwidth_autoswitch(dev);
dm_check_rfctrl_gpio(dev);
dm_check_rx_path_selection(dev);
dm_check_fsync(dev);
// Add by amy 2008-05-15 porting from windows code.
dm_check_pbc_gpio(dev);
dm_send_rssi_tofw(dev);
dm_ctstoself(dev);
} //HalDmWatchDog
#endif
/*
* Decide Rate Adaptive Set according to distance (signal strength)
@ -1595,37 +1544,15 @@ static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev)
}
#ifndef RTL8192SU
static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
// Tx Power tracking by Theremal Meter require Firmware R/W 3-wire. This mechanism
// can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w
// 3-wire by driver cause RF goes into wrong state.
if(priv->ieee80211->FwRWRF)
priv->btxpower_tracking = TRUE;
else
priv->btxpower_tracking = FALSE;
priv->txpower_count = 0;
priv->btxpower_trackingInit = FALSE;
}
#endif
void dm_initialize_txpower_tracking(struct net_device *dev)
{
#if (defined RTL8190P)
dm_InitializeTXPowerTracking_TSSI(dev);
#elif (defined RTL8192SU)
#else
// 2009/01/12 MH Enable for 92S series channel 1-14 CCK tx pwer setting for MP.
//
dm_InitializeTXPowerTracking_TSSI(dev);
#else
struct r8192_priv *priv = ieee80211_priv(dev);
if(priv->bDcut == TRUE)
dm_InitializeTXPowerTracking_TSSI(dev);
else
dm_InitializeTXPowerTracking_ThermalMeter(dev);
#endif
}// dm_InitializeTXPowerTracking
@ -1683,17 +1610,10 @@ static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
//Attention!! You have to wirte all 12bits data to RF, or it may cause RF to crash
//actually write reg0x02 bit1=0, then bit1=1.
//DbgPrint("Trigger ThermalMeter, write RF reg0x2 = 0x4d to 0x4f\n");
#ifdef RTL8192SU
rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bRFRegOffsetMask, 0x4d);
rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bRFRegOffsetMask, 0x4f);
rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bRFRegOffsetMask, 0x4d);
rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bRFRegOffsetMask, 0x4f);
#else
rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
#endif
TM_Trigger = 1;
return;
}
@ -2021,14 +1941,12 @@ extern void dm_change_dynamic_initgain_thresh(struct net_device *dev,
u32 dm_type,
u32 dm_value)
{
#ifdef RTL8192SU
struct r8192_priv *priv = ieee80211_priv(dev);
if(dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)
priv->MidHighPwrTHR_L2 = (u8)dm_value;
else if(dm_type == DIG_TYPE_THRESH_HIGHPWR_LOW)
priv->MidHighPwrTHR_L1 = (u8)dm_value;
return;
#endif
if (dm_type == DIG_TYPE_THRESH_HIGH)
{
dm_digtable.rssi_high_thresh = dm_value;
@ -2400,15 +2318,7 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
{
/* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
// 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
#ifdef RTL8192SU
rtl8192_setBBreg(dev, (rOFDM0_XATxAFE+3), bMaskByte0, 0x00);
#else
#ifdef RTL8190P
write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
#else
write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
#endif
#endif
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
*/
@ -2552,15 +2462,7 @@ static void dm_ctrl_initgain_byrssi_highpwr(
// 3.1 Higher PD_TH for OFDM for high power state.
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
{
#ifdef RTL8192SU
rtl8192_setBBreg(dev, (rOFDM0_XATxAFE+3), bMaskByte0, 0x10);
#else
#ifdef RTL8190P
write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
#else
write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
#endif
#endif
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
*/
@ -2727,15 +2629,7 @@ static void dm_pd_th(
{
/* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
// 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
#ifdef RTL8192SU
rtl8192_setBBreg(dev, (rOFDM0_XATxAFE+3), bMaskByte0, 0x00);
#else
#ifdef RTL8190P
write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
#else
write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
#endif
#endif
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
*/
@ -2899,7 +2793,6 @@ static void dm_check_edca_turbo(
{
curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
#ifdef RTL8192SU
// Modify EDCA parameters selection bias
// For some APs, use downlink EDCA parameters for uplink+downlink
if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_EDCA_BIAS_ON_RX)
@ -2942,31 +2835,6 @@ static void dm_check_edca_turbo(
}
priv->bcurrent_turbo_EDCA = true;
}
#else
// For RT-AP, we needs to turn it on when Rx>Tx
if(curRxOkCnt > 4*curTxOkCnt)
{
//printk("%s():curRxOkCnt > 4*curTxOkCnt\n");
if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
{
write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
priv->bis_cur_rdlstate = true;
}
}
else
{
//printk("%s():curRxOkCnt < 4*curTxOkCnt\n");
if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
{
write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
priv->bis_cur_rdlstate = false;
}
}
priv->bcurrent_turbo_EDCA = true;
#endif
}
else
{
@ -3212,9 +3080,7 @@ static void dm_check_rfctrl_gpio(struct net_device * dev)
#ifdef RTL8192U
return;
#endif
#ifdef RTL8192SU
return;
#endif
#ifdef RTL8192E
queue_delayed_work(priv->priv_wq,&priv->gpio_change_rf_wq,0);
#endif
@ -3257,7 +3123,6 @@ static void dm_check_pbc_gpio(struct net_device *dev)
priv->bpbc_pressed = true;
}
#endif
#ifdef RTL8192SU
struct r8192_priv *priv = ieee80211_priv(dev);
u8 tmp1byte;
@ -3283,7 +3148,6 @@ static void dm_check_pbc_gpio(struct net_device *dev)
priv->bpbc_pressed = true;
}
#endif
}
@ -3862,15 +3726,7 @@ extern void dm_fsync_timer_callback(unsigned long data)
write_nic_byte(dev, 0xC3e, 0x96);
}
priv->ContiuneDiffCount = 0;
#ifdef RTL8192SU
rtl8192_setBBreg(dev, rOFDM0_RxDetector2, bMaskDWord, 0x164052cd);
#else
#ifdef RTL8190P
write_nic_dword(dev, rOFDM0_RxDetector2, 0x164052cd);
#else
write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
#endif
#endif
}
RT_TRACE(COMP_HALDM, "ContiuneDiffCount %d\n", priv->ContiuneDiffCount);
RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);
@ -4283,16 +4139,6 @@ static void dm_dynamic_txpower(struct net_device *dev)
(priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low ) )
{
RT_TRACE(COMP_TXAGC,"SetTxPowerLevel8190() channel = %d \n" , priv->ieee80211->current_network.channel);
#ifndef RTL8192SU
#if defined(RTL8190P) || defined(RTL8192E)
SetTxPowerLevel8190(Adapter,pHalData->CurrentChannel);
#endif
#ifdef RTL8192U
rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
//pHalData->bStartTxCtrlByTPCNFR = FALSE; //Clear th flag of Set TX Power from Sitesurvey
#endif
#endif
}
priv->bLastDTPFlag_High = priv->bDynamicTxHighPower;
priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower;
@ -4306,11 +4152,7 @@ static void dm_check_txrateandretrycount(struct net_device * dev)
struct ieee80211_device* ieee = priv->ieee80211;
//for 11n tx rate
// priv->stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
#ifdef RTL8192SU
ieee->softmac_stats.CurrentShowTxate = read_nic_byte(dev, TX_RATE_REG);
#else
ieee->softmac_stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
#endif
//printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate);
//for initial tx rate
// priv->stats.last_packet_rate = read_nic_byte(dev, Initial_Tx_Rate_Reg);
@ -4322,24 +4164,6 @@ static void dm_check_txrateandretrycount(struct net_device * dev)
static void dm_send_rssi_tofw(struct net_device *dev)
{
#ifndef RTL8192SU
DCMD_TXCMD_T tx_cmd;
struct r8192_priv *priv = ieee80211_priv(dev);
// If we test chariot, we should stop the TX command ?
// Because 92E will always silent reset when we send tx command. We use register
// 0x1e0(byte) to botify driver.
write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);
return;
#if 1
tx_cmd.Op = TXCMD_SET_RX_RSSI;
tx_cmd.Length = 4;
tx_cmd.Value = priv->undecorated_smoothed_pwdb;
cmpk_message_handle_tx(dev, (u8*)&tx_cmd,
DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T));
#endif
#endif
}
#ifdef TO_DO_LIST

12
drivers/staging/rtl8192su/r8192U_wx.c
View file

@ -17,15 +17,9 @@
project Authors.
*/
#ifdef RTL8192SU
#include <linux/string.h>
#include "r8192U.h"
#include "r8192S_hw.h"
#else
#include <linux/string.h>
#include "r8192U.h"
#include "r8192U_hw.h"
#endif
#include "ieee80211/dot11d.h"
@ -344,7 +338,6 @@ static int r8192_wx_force_reset(struct net_device *dev,
}
#ifdef RTL8192SU
static int r8191su_wx_get_firm_version(struct net_device *dev,
struct iw_request_info *info,
struct iw_param *wrqu, char *extra)
@ -360,7 +353,6 @@ static int r8191su_wx_get_firm_version(struct net_device *dev,
up(&priv->wx_sem);
return 0;
}
#endif
@ -1232,14 +1224,12 @@ static const struct iw_priv_args r8192_private_args[] = {
IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "forcereset"
}
#ifdef RTL8192SU
,
{
SIOCIWFIRSTPRIV + 0x5,
IW_PRIV_TYPE_NONE, IW_PRIV_TYPE_INT|IW_PRIV_SIZE_FIXED|1,
"firm_ver"
}
#endif
};
@ -1262,9 +1252,7 @@ static iw_handler r8192_private_handler[] = {
#endif
r8192_wx_force_reset,
(iw_handler)NULL,
#ifdef RTL8192SU
(iw_handler)r8191su_wx_get_firm_version,
#endif
};
struct iw_statistics *r8192_get_wireless_stats(struct net_device *dev)

77
drivers/staging/rtl8192su/r819xU_cmdpkt.c
View file

@ -108,84 +108,7 @@ SendTxCommandPacket(
{
bool rt_status = true;
#ifdef RTL8192SU
return rt_status;
#else
#ifdef RTL8192U
return rt_status;
#else
struct r8192_priv *priv = ieee80211_priv(dev);
u16 frag_threshold;
u16 frag_length, frag_offset = 0;
//u16 total_size;
//int i;
rt_firmware *pfirmware = priv->pFirmware;
struct sk_buff *skb;
unsigned char *seg_ptr;
cb_desc *tcb_desc;
u8 bLastIniPkt;
firmware_init_param(dev);
//Fragmentation might be required
frag_threshold = pfirmware->cmdpacket_frag_thresold;
do {
if((buffer_len - frag_offset) > frag_threshold) {
frag_length = frag_threshold ;
bLastIniPkt = 0;
} else {
frag_length = buffer_len - frag_offset;
bLastIniPkt = 1;
}
/* Allocate skb buffer to contain firmware info and tx descriptor info
* add 4 to avoid packet appending overflow.
* */
#ifdef RTL8192U
skb = dev_alloc_skb(USB_HWDESC_HEADER_LEN + frag_length + 4);
#else
skb = dev_alloc_skb(frag_length + 4);
#endif
memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE);
tcb_desc->queue_index = TXCMD_QUEUE;
tcb_desc->bCmdOrInit = packettype;
tcb_desc->bLastIniPkt = bLastIniPkt;
#ifdef RTL8192U
skb_reserve(skb, USB_HWDESC_HEADER_LEN);
#endif
seg_ptr = skb_put(skb, buffer_len);
/*
* Transform from little endian to big endian
* and pending zero
*/
memcpy(seg_ptr,codevirtualaddress,buffer_len);
tcb_desc->txbuf_size= (u16)buffer_len;
if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)||
(!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\
(priv->ieee80211->queue_stop) ) {
RT_TRACE(COMP_FIRMWARE,"=====================================================> tx full!\n");
skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb);
} else {
priv->ieee80211->softmac_hard_start_xmit(skb,dev);
}
codevirtualaddress += frag_length;
frag_offset += frag_length;
}while(frag_offset < buffer_len);
return rt_status;
#endif
#endif
} /* CMPK_Message_Handle_Tx */
/*-----------------------------------------------------------------------------