mirror of
https://github.com/adulau/aha.git
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Blackfin: unify DMA masks
Every Blackfin variant has the same DMA bit masks, so avoid duplicating them over and over in each mach header. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
c6feb76828
commit
00d2460454
8 changed files with 50 additions and 301 deletions
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@ -16,36 +16,65 @@
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#define MAX_DMA_ADDRESS PAGE_OFFSET
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#define MAX_DMA_ADDRESS PAGE_OFFSET
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/*****************************************************************************
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/* DMA_CONFIG Masks */
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* Generic DMA Declarations
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#define DMAEN 0x0001 /* DMA Channel Enable */
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*
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#define WNR 0x0002 /* Channel Direction (W/R*) */
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****************************************************************************/
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#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
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#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
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#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
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#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
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#define RESTART 0x0020 /* DMA Buffer Clear */
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#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
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#define DI_EN 0x0080 /* Data Interrupt Enable */
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#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
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#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
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#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
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#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
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#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
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#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
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#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
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#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
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#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
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#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
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#define NDSIZE 0x0f00 /* Next Descriptor Size */
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#define DMAFLOW 0x7000 /* Flow Control */
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#define DMAFLOW_STOP 0x0000 /* Stop Mode */
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#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
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#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
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#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
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#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
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/* DMA_IRQ_STATUS Masks */
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#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
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#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
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#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
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#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
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/*-------------------------
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/*-------------------------
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* config reg bits value
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* config reg bits value
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*-------------------------*/
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*-------------------------*/
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#define DATA_SIZE_8 0
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#define DATA_SIZE_8 0
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#define DATA_SIZE_16 1
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#define DATA_SIZE_16 1
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#define DATA_SIZE_32 2
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#define DATA_SIZE_32 2
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#define DMA_FLOW_STOP 0
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#define DMA_FLOW_STOP 0
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#define DMA_FLOW_AUTO 1
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#define DMA_FLOW_AUTO 1
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#define DMA_FLOW_ARRAY 4
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#define DMA_FLOW_ARRAY 4
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#define DMA_FLOW_SMALL 6
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#define DMA_FLOW_SMALL 6
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#define DMA_FLOW_LARGE 7
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#define DMA_FLOW_LARGE 7
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#define DIMENSION_LINEAR 0
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#define DIMENSION_LINEAR 0
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#define DIMENSION_2D 1
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#define DIMENSION_2D 1
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#define DIR_READ 0
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#define DIR_READ 0
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#define DIR_WRITE 1
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#define DIR_WRITE 1
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#define INTR_DISABLE 0
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#define INTR_DISABLE 0
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#define INTR_ON_BUF 2
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#define INTR_ON_BUF 2
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#define INTR_ON_ROW 3
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#define INTR_ON_ROW 3
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#define DMA_NOSYNC_KEEP_DMA_BUF 0
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#define DMA_NOSYNC_KEEP_DMA_BUF 0
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#define DMA_SYNC_RESTART 1
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#define DMA_SYNC_RESTART 1
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struct dmasg {
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struct dmasg {
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void *next_desc_addr;
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void *next_desc_addr;
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@ -1260,33 +1260,6 @@
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/* ************************** DMA CONTROLLER MASKS ********************************/
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/* ************************** DMA CONTROLLER MASKS ********************************/
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/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
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#define DMAEN 0x0001 /* DMA Channel Enable */
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#define WNR 0x0002 /* Channel Direction (W/R*) */
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#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
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#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
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#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
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#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
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#define RESTART 0x0020 /* DMA Buffer Clear */
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#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
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#define DI_EN 0x0080 /* Data Interrupt Enable */
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#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
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#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
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#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
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#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
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#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
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#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
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#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
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#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
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#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
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#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
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#define NDSIZE 0x0900 /* Next Descriptor Size */
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#define DMAFLOW 0x7000 /* Flow Control */
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#define DMAFLOW_STOP 0x0000 /* Stop Mode */
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#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
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#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
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#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
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#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
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/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
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/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
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#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
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#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
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@ -1304,13 +1277,6 @@
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#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
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#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
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#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
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#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
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/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
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#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
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#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
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#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
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#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
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/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
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/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
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/* PPI_CONTROL Masks */
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/* PPI_CONTROL Masks */
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#define PORT_EN 0x0001 /* PPI Port Enable */
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#define PORT_EN 0x0001 /* PPI Port Enable */
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@ -1269,33 +1269,6 @@
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/* ************************** DMA CONTROLLER MASKS ********************************/
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/* ************************** DMA CONTROLLER MASKS ********************************/
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/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
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#define DMAEN 0x0001 /* DMA Channel Enable */
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#define WNR 0x0002 /* Channel Direction (W/R*) */
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#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
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#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
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#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
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#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
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#define RESTART 0x0020 /* DMA Buffer Clear */
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#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
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#define DI_EN 0x0080 /* Data Interrupt Enable */
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#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
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#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
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#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
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#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
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#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
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#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
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#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
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#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
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#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
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#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
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#define NDSIZE 0x0900 /* Next Descriptor Size */
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#define DMAFLOW 0x7000 /* Flow Control */
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#define DMAFLOW_STOP 0x0000 /* Stop Mode */
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#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
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#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
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#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
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#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
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/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
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/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
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#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
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#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
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#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
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#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
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#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
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#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
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/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
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#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
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#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
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#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
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#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
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/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
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/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
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/* PPI_CONTROL Masks */
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/* PPI_CONTROL Masks */
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#define PORT_EN 0x0001 /* PPI Port Enable */
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#define PORT_EN 0x0001 /* PPI Port Enable */
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/* ********** DMA CONTROLLER MASKS *********************8 */
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/* ********** DMA CONTROLLER MASKS *********************8 */
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/*DMAx_CONFIG, MDMA_yy_CONFIG Masks */
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/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
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#define DMAEN 0x00000001 /* Channel Enable */
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#define WNR 0x00000002 /* Channel Direction (W/R*) */
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#define WDSIZE_8 0x00000000 /* Word Size 8 bits */
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#define WDSIZE_16 0x00000004 /* Word Size 16 bits */
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#define WDSIZE_32 0x00000008 /* Word Size 32 bits */
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#define DMA2D 0x00000010 /* 2D/1D* Mode */
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#define RESTART 0x00000020 /* Restart */
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#define DI_SEL 0x00000040 /* Data Interrupt Select */
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#define DI_EN 0x00000080 /* Data Interrupt Enable */
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#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
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#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
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#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
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#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
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#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
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#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
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#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
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#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
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#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
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#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
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#define NDSIZE 0x00000900 /* Next Descriptor Size */
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#define DMAFLOW 0x00007000 /* Flow Control */
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#define DMAFLOW_STOP 0x0000 /* Stop Mode */
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#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
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#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
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#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
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#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
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#define DMAEN_P 0 /* Channel Enable */
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#define WNR_P 1 /* Channel Direction (W/R*) */
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#define DMA2D_P 4 /* 2D/1D* Mode */
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#define RESTART_P 5 /* Restart */
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#define DI_SEL_P 6 /* Data Interrupt Select */
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#define DI_EN_P 7 /* Data Interrupt Enable */
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/*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
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#define DMA_DONE 0x00000001 /* DMA Done Indicator */
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#define DMA_ERR 0x00000002 /* DMA Error Indicator */
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#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
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#define DMA_RUN 0x00000008 /* DMA Running Indicator */
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#define DMA_DONE_P 0 /* DMA Done Indicator */
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#define DMA_ERR_P 1 /* DMA Error Indicator */
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#define DFETCH_P 2 /* Descriptor Fetch Indicator */
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#define DMA_RUN_P 3 /* DMA Running Indicator */
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/*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
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#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
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#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
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#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
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#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
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#define BGSTAT 0x0020 /* Bus Grant Status */
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#define BGSTAT 0x0020 /* Bus Grant Status */
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/* ************************** DMA CONTROLLER MASKS ********************************/
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/* ************************** DMA CONTROLLER MASKS ********************************/
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/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
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#define DMAEN 0x0001 /* DMA Channel Enable */
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#define WNR 0x0002 /* Channel Direction (W/R*) */
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#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
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#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
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#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
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#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
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#define RESTART 0x0020 /* DMA Buffer Clear */
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#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
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#define DI_EN 0x0080 /* Data Interrupt Enable */
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#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
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#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
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#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
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#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
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#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
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#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
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#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
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#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
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#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
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#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
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#define NDSIZE 0x0900 /* Next Descriptor Size */
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#define DMAFLOW 0x7000 /* Flow Control */
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#define DMAFLOW_STOP 0x0000 /* Stop Mode */
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#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
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#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
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#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
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#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
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/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
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/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
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#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
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#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
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#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
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#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
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#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
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#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
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/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
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#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
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#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
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#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
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#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
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/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
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/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
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/* PPI_CONTROL Masks */
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/* PPI_CONTROL Masks */
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#define PORT_EN 0x0001 /* PPI Port Enable */
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#define PORT_EN 0x0001 /* PPI Port Enable */
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/* ********** DMA CONTROLLER MASKS ***********************/
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/* ********** DMA CONTROLLER MASKS ***********************/
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/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
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#define DMAEN 0x0001 /* Channel Enable */
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#define WNR 0x0002 /* Channel Direction (W/R*) */
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#define WDSIZE_8 0x0000 /* Word Size 8 bits */
|
|
||||||
#define WDSIZE_16 0x0004 /* Word Size 16 bits */
|
|
||||||
#define WDSIZE_32 0x0008 /* Word Size 32 bits */
|
|
||||||
#define DMA2D 0x0010 /* 2D/1D* Mode */
|
|
||||||
#define RESTART 0x0020 /* Restart */
|
|
||||||
#define DI_SEL 0x0040 /* Data Interrupt Select */
|
|
||||||
#define DI_EN 0x0080 /* Data Interrupt Enable */
|
|
||||||
#define NDSIZE 0x0900 /* Next Descriptor Size */
|
|
||||||
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
|
|
||||||
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
|
|
||||||
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
|
|
||||||
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
|
|
||||||
#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
|
|
||||||
#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
|
|
||||||
#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
|
|
||||||
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
|
|
||||||
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
|
|
||||||
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
|
|
||||||
|
|
||||||
#define DMAFLOW 0x7000 /* Flow Control */
|
|
||||||
#define DMAFLOW_STOP 0x0000 /* Stop Mode */
|
|
||||||
#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
|
|
||||||
#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
|
|
||||||
#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
|
|
||||||
#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
|
|
||||||
|
|
||||||
#define DMAEN_P 0x0 /* Channel Enable */
|
|
||||||
#define WNR_P 0x1 /* Channel Direction (W/R*) */
|
|
||||||
#define DMA2D_P 0x4 /* 2D/1D* Mode */
|
|
||||||
#define RESTART_P 0x5 /* Restart */
|
|
||||||
#define DI_SEL_P 0x6 /* Data Interrupt Select */
|
|
||||||
#define DI_EN_P 0x7 /* Data Interrupt Enable */
|
|
||||||
|
|
||||||
/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
|
|
||||||
#define DMA_DONE 0x0001 /* DMA Done Indicator */
|
|
||||||
#define DMA_ERR 0x0002 /* DMA Error Indicator */
|
|
||||||
#define DFETCH 0x0004 /* Descriptor Fetch Indicator */
|
|
||||||
#define DMA_RUN 0x0008 /* DMA Running Indicator */
|
|
||||||
|
|
||||||
#define DMA_DONE_P 0x0 /* DMA Done Indicator */
|
|
||||||
#define DMA_ERR_P 0x1 /* DMA Error Indicator */
|
|
||||||
#define DFETCH_P 0x2 /* Descriptor Fetch Indicator */
|
|
||||||
#define DMA_RUN_P 0x3 /* DMA Running Indicator */
|
|
||||||
|
|
||||||
/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
|
/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1609,44 +1609,6 @@
|
||||||
#define PINT2 0x40000000 /* Pin Interrupt 2 */
|
#define PINT2 0x40000000 /* Pin Interrupt 2 */
|
||||||
#define PINT3 0x80000000 /* Pin Interrupt 3 */
|
#define PINT3 0x80000000 /* Pin Interrupt 3 */
|
||||||
|
|
||||||
/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
|
|
||||||
|
|
||||||
#define DMAEN 0x1 /* DMA Channel Enable */
|
|
||||||
#define WNR 0x2 /* DMA Direction */
|
|
||||||
#define WDSIZE_8 0x0 /* Transfer Word Size = 8 */
|
|
||||||
#define WDSIZE_16 0x4 /* Transfer Word Size = 16 */
|
|
||||||
#define WDSIZE_32 0x8 /* Transfer Word Size = 32 */
|
|
||||||
#define DMA2D 0x10 /* DMA Mode */
|
|
||||||
#define RESTART 0x20 /* Work Unit Transitions */
|
|
||||||
#define DI_SEL 0x40 /* Data Interrupt Timing Select */
|
|
||||||
#define DI_EN 0x80 /* Data Interrupt Enable */
|
|
||||||
|
|
||||||
#define NDSIZE 0xf00 /* Flex Descriptor Size */
|
|
||||||
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
|
|
||||||
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
|
|
||||||
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
|
|
||||||
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
|
|
||||||
#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
|
|
||||||
#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
|
|
||||||
#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
|
|
||||||
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
|
|
||||||
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
|
|
||||||
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
|
|
||||||
|
|
||||||
#define DMAFLOW 0xf000 /* Next Operation */
|
|
||||||
#define DMAFLOW_STOP 0x0000 /* Stop Mode */
|
|
||||||
#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
|
|
||||||
#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
|
|
||||||
#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
|
|
||||||
#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
|
|
||||||
|
|
||||||
/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
|
|
||||||
|
|
||||||
#define DMA_DONE 0x1 /* DMA Completion Interrupt Status */
|
|
||||||
#define DMA_ERR 0x2 /* DMA Error Interrupt Status */
|
|
||||||
#define DFETCH 0x4 /* DMA Descriptor Fetch */
|
|
||||||
#define DMA_RUN 0x8 /* DMA Channel Running */
|
|
||||||
|
|
||||||
/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
|
/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
|
||||||
|
|
||||||
#define CTYPE 0x40 /* DMA Channel Type */
|
#define CTYPE 0x40 /* DMA Channel Type */
|
||||||
|
|
|
||||||
|
|
@ -1096,53 +1096,6 @@
|
||||||
|
|
||||||
/* ********** DMA CONTROLLER MASKS *********************8 */
|
/* ********** DMA CONTROLLER MASKS *********************8 */
|
||||||
|
|
||||||
/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */
|
|
||||||
#define DMAEN 0x00000001 /* Channel Enable */
|
|
||||||
#define WNR 0x00000002 /* Channel Direction (W/R*) */
|
|
||||||
#define WDSIZE_8 0x00000000 /* Word Size 8 bits */
|
|
||||||
#define WDSIZE_16 0x00000004 /* Word Size 16 bits */
|
|
||||||
#define WDSIZE_32 0x00000008 /* Word Size 32 bits */
|
|
||||||
#define DMA2D 0x00000010 /* 2D/1D* Mode */
|
|
||||||
#define RESTART 0x00000020 /* Restart */
|
|
||||||
#define DI_SEL 0x00000040 /* Data Interrupt Select */
|
|
||||||
#define DI_EN 0x00000080 /* Data Interrupt Enable */
|
|
||||||
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
|
|
||||||
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
|
|
||||||
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
|
|
||||||
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
|
|
||||||
#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
|
|
||||||
#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
|
|
||||||
#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
|
|
||||||
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
|
|
||||||
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
|
|
||||||
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
|
|
||||||
#define NDSIZE 0x00000900 /* Next Descriptor Size */
|
|
||||||
#define DMAFLOW 0x00007000 /* Flow Control */
|
|
||||||
#define DMAFLOW_STOP 0x0000 /* Stop Mode */
|
|
||||||
#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
|
|
||||||
#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
|
|
||||||
#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
|
|
||||||
#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
|
|
||||||
|
|
||||||
#define DMAEN_P 0 /* Channel Enable */
|
|
||||||
#define WNR_P 1 /* Channel Direction (W/R*) */
|
|
||||||
#define DMA2D_P 4 /* 2D/1D* Mode */
|
|
||||||
#define RESTART_P 5 /* Restart */
|
|
||||||
#define DI_SEL_P 6 /* Data Interrupt Select */
|
|
||||||
#define DI_EN_P 7 /* Data Interrupt Enable */
|
|
||||||
|
|
||||||
/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */
|
|
||||||
|
|
||||||
#define DMA_DONE 0x00000001 /* DMA Done Indicator */
|
|
||||||
#define DMA_ERR 0x00000002 /* DMA Error Indicator */
|
|
||||||
#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
|
|
||||||
#define DMA_RUN 0x00000008 /* DMA Running Indicator */
|
|
||||||
|
|
||||||
#define DMA_DONE_P 0 /* DMA Done Indicator */
|
|
||||||
#define DMA_ERR_P 1 /* DMA Error Indicator */
|
|
||||||
#define DFETCH_P 2 /* Descriptor Fetch Indicator */
|
|
||||||
#define DMA_RUN_P 3 /* DMA Running Indicator */
|
|
||||||
|
|
||||||
/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
|
/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
|
||||||
|
|
||||||
#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
|
#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue