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107 lines
2 KiB
C
107 lines
2 KiB
C
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/*
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* linux/asm/assembler.h
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*
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* This file contains arm architecture specific defines
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* for the different processors.
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*
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* Do not include any C declarations in this file - it is included by
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* assembler source.
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*/
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#ifndef __ASSEMBLY__
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#error "Only include this from assembly code"
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#endif
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/*
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* Endian independent macros for shifting bytes within registers.
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*/
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#define pull lsr
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#define push lsl
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#define byte(x) (x*8)
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#ifdef __STDC__
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#define LOADREGS(cond, base, reglist...)\
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ldm##cond base,reglist^
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#define RETINSTR(instr, regs...)\
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instr##s regs
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#else
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#define LOADREGS(cond, base, reglist...)\
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ldm/**/cond base,reglist^
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#define RETINSTR(instr, regs...)\
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instr/**/s regs
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#endif
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#define MODENOP\
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mov r0, r0
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#define MODE(savereg,tmpreg,mode) \
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mov savereg, pc; \
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bic tmpreg, savereg, $0x0c000003; \
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orr tmpreg, tmpreg, $mode; \
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teqp tmpreg, $0
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#define RESTOREMODE(savereg) \
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teqp savereg, $0
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#define SAVEIRQS(tmpreg)
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#define RESTOREIRQS(tmpreg)
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#define DISABLEIRQS(tmpreg)\
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teqp pc, $0x08000003
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#define ENABLEIRQS(tmpreg)\
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teqp pc, $0x00000003
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#define USERMODE(tmpreg)\
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teqp pc, $0x00000000;\
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mov r0, r0
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#define SVCMODE(tmpreg)\
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teqp pc, $0x00000003;\
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mov r0, r0
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/*
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* Save the current IRQ state and disable IRQs
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* Note that this macro assumes FIQs are enabled, and
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* that the processor is in SVC mode.
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*/
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.macro save_and_disable_irqs, oldcpsr, temp
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mov \oldcpsr, pc
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orr \temp, \oldcpsr, #0x08000000
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teqp \temp, #0
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.endm
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/*
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* Restore interrupt state previously stored in
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* a register
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* ** Actually do nothing on Arc - hope that the caller uses a MOVS PC soon
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* after!
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*/
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.macro restore_irqs, oldcpsr
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@ This be restore_irqs
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.endm
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/*
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* These two are used to save LR/restore PC over a user-based access.
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* The old 26-bit architecture requires that we save lr (R14)
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*/
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.macro save_lr
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str lr, [sp, #-4]!
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.endm
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.macro restore_pc
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ldmfd sp!, {pc}^
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.endm
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#define USER(x...) \
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9999: x; \
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.section __ex_table,"a"; \
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.align 3; \
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.long 9999b,9001f; \
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.previous
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